Re: [Xen-devel] [PATCH v3] x86/EPT: work around hardware erratum setting A bit

2015-10-13 Thread Kai Huang
On 10/02/2015 05:36 PM, Wei Liu wrote: On Wed, Sep 30, 2015 at 01:25:49PM +0100, Wei Liu wrote: On Wed, Sep 30, 2015 at 05:36:22AM -0600, Jan Beulich wrote: Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for log-dirty"), the A and D bits of EPT paging entries are set unconditional

Re: [Xen-devel] [PATCH v3] x86/EPT: work around hardware erratum setting A bit

2015-10-02 Thread Wei Liu
On Fri, Oct 02, 2015 at 11:29:54AM +0100, Andrew Cooper wrote: > On 30/09/15 12:47, Andrew Cooper wrote: > > On 30/09/15 12:36, Jan Beulich wrote: > >> Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for > >> log-dirty"), the A and D bits of EPT paging entries are set > >> unconditionall

Re: [Xen-devel] [PATCH v3] x86/EPT: work around hardware erratum setting A bit

2015-10-02 Thread Andrew Cooper
On 30/09/15 12:47, Andrew Cooper wrote: > On 30/09/15 12:36, Jan Beulich wrote: >> Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for >> log-dirty"), the A and D bits of EPT paging entries are set >> unconditionally, regardless of whether PML is enabled or not. This >> causes a regressi

Re: [Xen-devel] [PATCH v3] x86/EPT: work around hardware erratum setting A bit

2015-10-02 Thread Wei Liu
On Wed, Sep 30, 2015 at 01:25:49PM +0100, Wei Liu wrote: > On Wed, Sep 30, 2015 at 05:36:22AM -0600, Jan Beulich wrote: > > Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for > > log-dirty"), the A and D bits of EPT paging entries are set > > unconditionally, regardless of whether PML i

Re: [Xen-devel] [PATCH v3] x86/EPT: work around hardware erratum setting A bit

2015-09-30 Thread Wei Liu
On Wed, Sep 30, 2015 at 05:36:22AM -0600, Jan Beulich wrote: > Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for > log-dirty"), the A and D bits of EPT paging entries are set > unconditionally, regardless of whether PML is enabled or not. This > causes a regression in Xen 4.6 on some p

Re: [Xen-devel] [PATCH v3] x86/EPT: work around hardware erratum setting A bit

2015-09-30 Thread Andrew Cooper
On 30/09/15 13:02, Jan Beulich wrote: On 30.09.15 at 13:47, wrote: >> On 30/09/15 12:36, Jan Beulich wrote: >>> Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for >>> log-dirty"), the A and D bits of EPT paging entries are set >>> unconditionally, regardless of whether PML is enab

Re: [Xen-devel] [PATCH v3] x86/EPT: work around hardware erratum setting A bit

2015-09-30 Thread Jan Beulich
>>> On 30.09.15 at 13:47, wrote: > On 30/09/15 12:36, Jan Beulich wrote: >> Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for >> log-dirty"), the A and D bits of EPT paging entries are set >> unconditionally, regardless of whether PML is enabled or not. This >> causes a regression in

Re: [Xen-devel] [PATCH v3] x86/EPT: work around hardware erratum setting A bit

2015-09-30 Thread Andrew Cooper
On 30/09/15 12:36, Jan Beulich wrote: > Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for > log-dirty"), the A and D bits of EPT paging entries are set > unconditionally, regardless of whether PML is enabled or not. This > causes a regression in Xen 4.6 on some processors due to Intel

[Xen-devel] [PATCH v3] x86/EPT: work around hardware erratum setting A bit

2015-09-30 Thread Jan Beulich
Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for log-dirty"), the A and D bits of EPT paging entries are set unconditionally, regardless of whether PML is enabled or not. This causes a regression in Xen 4.6 on some processors due to Intel Errata AVR41 -- HVM guests get severe memory c