Hi Andre,
On 06/04/17 15:37, Andre Przywara wrote:
On 06/04/17 13:58, Julien Grall wrote:
Hi Andre,
On 06/04/17 00:18, Andre Przywara wrote:
+static unsigned int max_lpi_bits = 20;
+integer_param("max_lpi_bits", max_lpi_bits);
+
+int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits)
+{
+
Hi,
On 06/04/17 13:58, Julien Grall wrote:
> Hi Andre,
>
> On 06/04/17 00:18, Andre Przywara wrote:
>> +static unsigned int max_lpi_bits = 20;
>> +integer_param("max_lpi_bits", max_lpi_bits);
>> +
>> +int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits)
>> +{
>> +/* An implementation need
Hi Andre,
On 06/04/17 00:18, Andre Przywara wrote:
+static unsigned int max_lpi_bits = 20;
+integer_param("max_lpi_bits", max_lpi_bits);
+
+int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits)
+{
+/* An implementation needs to support at least 14 bits of LPI IDs. */
+max_lpi_bits = m
On Thu, 6 Apr 2017, Andre Przywara wrote:
> The ARM GICv3 provides a new kind of interrupt called LPIs.
> The pending bits and the configuration data (priority, enable bits) for
> those LPIs are stored in tables in normal memory, which software has to
> provide to the hardware.
> Allocate the requi
The ARM GICv3 provides a new kind of interrupt called LPIs.
The pending bits and the configuration data (priority, enable bits) for
those LPIs are stored in tables in normal memory, which software has to
provide to the hardware.
Allocate the required memory, initialize it and hand it over to each
r
