2015-03-03 15:42 GMT+00:00 Julien Grall julien.gr...@linaro.org:
On 03/03/15 15:36, Frediano Ziglio wrote:
Hello Frediano,
On 03/03/15 11:19, Frediano Ziglio wrote:
The GIC in this platform is mainly compatible with the standard
GICv2 beside:
- ITARGET is extended to 16 bit to support 16
On 03/03/15 15:36, Frediano Ziglio wrote:
Hello Frediano,
On 03/03/15 11:19, Frediano Ziglio wrote:
The GIC in this platform is mainly compatible with the standard
GICv2 beside:
- ITARGET is extended to 16 bit to support 16 CPUs;
- SGI mask is extended to support 16 CPUs;
- maximum
Hello Frediano,
On 03/03/15 11:19, Frediano Ziglio wrote:
The GIC in this platform is mainly compatible with the standard
GICv2 beside:
- ITARGET is extended to 16 bit to support 16 CPUs;
- SGI mask is extended to support 16 CPUs;
- maximum supported interrupt is 510;
510 is not
Hello Frediano,
On 03/03/15 11:19, Frediano Ziglio wrote:
The GIC in this platform is mainly compatible with the standard
GICv2 beside:
- ITARGET is extended to 16 bit to support 16 CPUs;
- SGI mask is extended to support 16 CPUs;
- maximum supported interrupt is 510;
510 is not a multiple
The GIC in this platform is mainly compatible with the standard
GICv2 beside:
- ITARGET is extended to 16 bit to support 16 CPUs;
- SGI mask is extended to support 16 CPUs;
- maximum supported interrupt is 510;
- GICH APR and LR register offsets.
Signed-off-by: Frediano Ziglio
