Hi Andre,
On 15/11/16 11:32, Andre Przywara wrote:
On 01/11/16 17:22, Julien Grall wrote:
On 28/09/2016 19:24, Andre Przywara wrote:
The ARM GICv3 ITS provides a new kind of interrupt called LPIs.
The pending bits and the configuration data (priority, enable bits) for
those LPIs are stored in
Hi Julien,
On 01/11/16 17:22, Julien Grall wrote:
> Hi Andre,
>
> On 28/09/2016 19:24, Andre Przywara wrote:
>> The ARM GICv3 ITS provides a new kind of interrupt called LPIs.
>> The pending bits and the configuration data (priority, enable bits) for
>> those LPIs are stored in tables in normal m
On Thu, 10 Nov 2016, Andre Przywara wrote:
> Hi,
>
> On 26/10/16 02:10, Stefano Stabellini wrote:
> > Hi Andre,
> >
> > Sorry for the late reply, I'll try to be faster for the next rounds of
> > review. The patch looks good for a first iteration. Some comments below.
>
> No worries and thanks fo
Hi,
On 26/10/16 02:10, Stefano Stabellini wrote:
> Hi Andre,
>
> Sorry for the late reply, I'll try to be faster for the next rounds of
> review. The patch looks good for a first iteration. Some comments below.
No worries and thanks for the thorough review, much appreciated.
As you can see I too
On 24/10/16 15:28, Vijay Kilari wrote:
Hi Vijay,
thanks for having a look!
> On Wed, Sep 28, 2016 at 11:54 PM, Andre Przywara
> wrote:
>> The ARM GICv3 ITS provides a new kind of interrupt called LPIs.
>> The pending bits and the configuration data (priority, enable bits) for
>> those LPIs are
Hi Andre,
On 28/09/2016 19:24, Andre Przywara wrote:
The ARM GICv3 ITS provides a new kind of interrupt called LPIs.
The pending bits and the configuration data (priority, enable bits) for
those LPIs are stored in tables in normal memory, which software has to
provide to the hardware.
Allocate t
Hi Andre,
Sorry for the late reply, I'll try to be faster for the next rounds of
review. The patch looks good for a first iteration. Some comments below.
On Wed, 28 Sep 2016, Andre Przywara wrote:
> The ARM GICv3 ITS provides a new kind of interrupt called LPIs.
> The pending bits and the configu
On Wed, Sep 28, 2016 at 11:54 PM, Andre Przywara wrote:
> The ARM GICv3 ITS provides a new kind of interrupt called LPIs.
> The pending bits and the configuration data (priority, enable bits) for
> those LPIs are stored in tables in normal memory, which software has to
> provide to the hardware.
>
The ARM GICv3 ITS provides a new kind of interrupt called LPIs.
The pending bits and the configuration data (priority, enable bits) for
those LPIs are stored in tables in normal memory, which software has to
provide to the hardware.
Allocate the required memory, initialize it and hand it over to ea
