Hello Sameer,
On 19/05/17 07:38, Goel, Sameer wrote:
On 12/29/2016 7:04 AM, Julien Grall wrote:
### Finding the StreamID and DeviceID
The static table IORT (see [5]) will provide information that will help to
deduce the StreamID and DeviceID from a given RID.
IORT table will also need s
On 12/29/2016 7:04 AM, Julien Grall wrote:
>
> ### Finding the StreamID and DeviceID
>
> The static table IORT (see [5]) will provide information that will help to
> deduce the StreamID and DeviceID from a given RID.
>
IORT table will also need some information on PCI seg to parse through the
Hi Roger,
On 15/03/17 16:38, Roger Pau Monn? wrote:
On Wed, Mar 15, 2017 at 10:11:35AM -0500, Venu Busireddy wrote:
On Wed, Mar 15, 2017 at 12:56:50PM +, Roger Pau Monn? wrote:
On Wed, Mar 15, 2017 at 08:42:04AM -0400, Konrad Rzeszutek Wilk wrote:
On Wed, Mar 15, 2017 at 12:07:28PM +,
Hi Roger,
Sorry for the late answer.
On 15/03/17 17:00, Roger Pau Monn? wrote:
On Wed, Mar 15, 2017 at 11:54:07AM -0500, Venu Busireddy wrote:
On Wed, Mar 15, 2017 at 04:38:39PM +, Roger Pau Monn? wrote:
On Wed, Mar 15, 2017 at 10:11:35AM -0500, Venu Busireddy wrote:
On Wed, Mar 15, 2017
On Wed, Mar 15, 2017 at 11:54:07AM -0500, Venu Busireddy wrote:
> On Wed, Mar 15, 2017 at 04:38:39PM +, Roger Pau Monn? wrote:
> > On Wed, Mar 15, 2017 at 10:11:35AM -0500, Venu Busireddy wrote:
> > > On Wed, Mar 15, 2017 at 12:56:50PM +, Roger Pau Monn? wrote:
> > > > On Wed, Mar 15, 2017
On Wed, Mar 15, 2017 at 04:38:39PM +, Roger Pau Monn? wrote:
> On Wed, Mar 15, 2017 at 10:11:35AM -0500, Venu Busireddy wrote:
> > On Wed, Mar 15, 2017 at 12:56:50PM +, Roger Pau Monn? wrote:
> > > On Wed, Mar 15, 2017 at 08:42:04AM -0400, Konrad Rzeszutek Wilk wrote:
> > > > On Wed, Mar 15
On Wed, Mar 15, 2017 at 10:11:35AM -0500, Venu Busireddy wrote:
> On Wed, Mar 15, 2017 at 12:56:50PM +, Roger Pau Monn? wrote:
> > On Wed, Mar 15, 2017 at 08:42:04AM -0400, Konrad Rzeszutek Wilk wrote:
> > > On Wed, Mar 15, 2017 at 12:07:28PM +, Roger Pau Monn? wrote:
> > > > On Fri, Mar 10
On Wed, Mar 15, 2017 at 12:56:50PM +, Roger Pau Monn? wrote:
> On Wed, Mar 15, 2017 at 08:42:04AM -0400, Konrad Rzeszutek Wilk wrote:
> > On Wed, Mar 15, 2017 at 12:07:28PM +, Roger Pau Monn? wrote:
> > > On Fri, Mar 10, 2017 at 10:28:43AM -0500, Konrad Rzeszutek Wilk wrote:
> > > > On Fri,
On Wed, Mar 15, 2017 at 08:42:04AM -0400, Konrad Rzeszutek Wilk wrote:
> On Wed, Mar 15, 2017 at 12:07:28PM +, Roger Pau Monné wrote:
> > On Fri, Mar 10, 2017 at 10:28:43AM -0500, Konrad Rzeszutek Wilk wrote:
> > > On Fri, Mar 10, 2017 at 12:23:18PM +0900, Roger Pau Monné wrote:
> > > > On Thu,
On Wed, Mar 15, 2017 at 12:07:28PM +, Roger Pau Monné wrote:
> On Fri, Mar 10, 2017 at 10:28:43AM -0500, Konrad Rzeszutek Wilk wrote:
> > On Fri, Mar 10, 2017 at 12:23:18PM +0900, Roger Pau Monné wrote:
> > > On Thu, Mar 09, 2017 at 07:29:34PM -0500, Konrad Rzeszutek Wilk wrote:
> > > > On Thu,
On Fri, Mar 10, 2017 at 10:28:43AM -0500, Konrad Rzeszutek Wilk wrote:
> On Fri, Mar 10, 2017 at 12:23:18PM +0900, Roger Pau Monné wrote:
> > On Thu, Mar 09, 2017 at 07:29:34PM -0500, Konrad Rzeszutek Wilk wrote:
> > > On Thu, Mar 09, 2017 at 01:26:45PM +, Julien Grall wrote:
> > > > Hi Konrad,
On Fri, Mar 10, 2017 at 12:23:18PM +0900, Roger Pau Monné wrote:
> On Thu, Mar 09, 2017 at 07:29:34PM -0500, Konrad Rzeszutek Wilk wrote:
> > On Thu, Mar 09, 2017 at 01:26:45PM +, Julien Grall wrote:
> > > Hi Konrad,
> > >
> > > On 09/03/17 11:17, Konrad Rzeszutek Wilk wrote:
> > > > On Thu, M
On Thu, Mar 09, 2017 at 07:29:34PM -0500, Konrad Rzeszutek Wilk wrote:
> On Thu, Mar 09, 2017 at 01:26:45PM +, Julien Grall wrote:
> > Hi Konrad,
> >
> > On 09/03/17 11:17, Konrad Rzeszutek Wilk wrote:
> > > On Thu, Mar 09, 2017 at 11:59:51AM +0900, Roger Pau Monné wrote:
> > > > On Wed, Mar 0
On Thu, Mar 09, 2017 at 01:26:45PM +, Julien Grall wrote:
> Hi Konrad,
>
> On 09/03/17 11:17, Konrad Rzeszutek Wilk wrote:
> > On Thu, Mar 09, 2017 at 11:59:51AM +0900, Roger Pau Monné wrote:
> > > On Wed, Mar 08, 2017 at 02:12:09PM -0500, Konrad Rzeszutek Wilk wrote:
> > > > On Wed, Mar 08, 2
Hi Konrad,
On 09/03/17 11:17, Konrad Rzeszutek Wilk wrote:
On Thu, Mar 09, 2017 at 11:59:51AM +0900, Roger Pau Monné wrote:
On Wed, Mar 08, 2017 at 02:12:09PM -0500, Konrad Rzeszutek Wilk wrote:
On Wed, Mar 08, 2017 at 07:06:23PM +, Julien Grall wrote:
Hi,
On 02/02/17 23:06, Stefano Stab
On Thu, Mar 09, 2017 at 11:59:51AM +0900, Roger Pau Monné wrote:
> On Wed, Mar 08, 2017 at 02:12:09PM -0500, Konrad Rzeszutek Wilk wrote:
> > On Wed, Mar 08, 2017 at 07:06:23PM +, Julien Grall wrote:
> > > Hi,
> > >
> > > On 02/02/17 23:06, Stefano Stabellini wrote:
> > > > On Thu, 2 Feb 2017,
On Wed, Mar 08, 2017 at 02:12:09PM -0500, Konrad Rzeszutek Wilk wrote:
> On Wed, Mar 08, 2017 at 07:06:23PM +, Julien Grall wrote:
> > Hi,
> >
> > On 02/02/17 23:06, Stefano Stabellini wrote:
> > > On Thu, 2 Feb 2017, Julien Grall wrote:
> > > > On 01/02/17 10:55, Roger Pau Monné wrote:
> > >
Hi Stefano,
On 08/03/2017 19:55, Stefano Stabellini wrote:
On Wed, 8 Mar 2017, Konrad Rzeszutek Wilk wrote:
On Wed, Mar 08, 2017 at 07:06:23PM +, Julien Grall wrote:
Hi,
On 02/02/17 23:06, Stefano Stabellini wrote:
On Thu, 2 Feb 2017, Julien Grall wrote:
On 01/02/17 10:55, Roger Pau Mon
On Wed, 8 Mar 2017, Konrad Rzeszutek Wilk wrote:
> On Wed, Mar 08, 2017 at 07:06:23PM +, Julien Grall wrote:
> > Hi,
> >
> > On 02/02/17 23:06, Stefano Stabellini wrote:
> > > On Thu, 2 Feb 2017, Julien Grall wrote:
> > > > On 01/02/17 10:55, Roger Pau Monné wrote:
> > > > > On Wed, Jan 25, 20
On Wed, Mar 08, 2017 at 07:06:23PM +, Julien Grall wrote:
> Hi,
>
> On 02/02/17 23:06, Stefano Stabellini wrote:
> > On Thu, 2 Feb 2017, Julien Grall wrote:
> > > On 01/02/17 10:55, Roger Pau Monné wrote:
> > > > On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
> > > > > On 24/01/
Hi,
On 02/02/17 23:06, Stefano Stabellini wrote:
On Thu, 2 Feb 2017, Julien Grall wrote:
On 01/02/17 10:55, Roger Pau Monné wrote:
On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
On 24/01/17 20:07, Stefano Stabellini wrote:
On Tue, 24 Jan 2017, Julien Grall wrote:
For DT, I wo
On Thu, Feb 23, 2017 at 04:47:19PM +, Julien Grall wrote:
>
> Hi Edgar,
>
> On 22/02/17 04:03, Edgar E. Iglesias wrote:
> >On Mon, Feb 13, 2017 at 03:35:19PM +, Julien Grall wrote:
> >>On 02/02/17 15:33, Edgar E. Iglesias wrote:
> >>>On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall
Hi Edgar,
On 22/02/17 04:03, Edgar E. Iglesias wrote:
On Mon, Feb 13, 2017 at 03:35:19PM +, Julien Grall wrote:
On 02/02/17 15:33, Edgar E. Iglesias wrote:
On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall wrote:
On 31/01/2017 19:06, Edgar E. Iglesias wrote:
On Tue, Jan 31, 2017 at
On Mon, Feb 13, 2017 at 03:35:19PM +, Julien Grall wrote:
> On 02/02/17 15:33, Edgar E. Iglesias wrote:
> >On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall wrote:
> >>On 31/01/2017 19:06, Edgar E. Iglesias wrote:
> >>>On Tue, Jan 31, 2017 at 05:09:53PM +, Julien Grall wrote:
> >>Thank
Hi Stefano,
On 02/14/2017 06:20 PM, Stefano Stabellini wrote:
On Tue, 14 Feb 2017, Julien Grall wrote:
Hi Stefano,
On 02/13/2017 07:59 PM, Stefano Stabellini wrote:
On Mon, 13 Feb 2017, Julien Grall wrote:
Hi Stefano,
On 10/02/17 01:01, Stefano Stabellini wrote:
On Fri, 3 Feb 2017, Edgar E
On Tue, 14 Feb 2017, Julien Grall wrote:
> Hi Stefano,
>
> On 02/13/2017 07:59 PM, Stefano Stabellini wrote:
> > On Mon, 13 Feb 2017, Julien Grall wrote:
> >> Hi Stefano,
> >>
> >> On 10/02/17 01:01, Stefano Stabellini wrote:
> >>> On Fri, 3 Feb 2017, Edgar E. Iglesias wrote:
> A possible hac
Hi Stefano,
On 02/13/2017 07:59 PM, Stefano Stabellini wrote:
> On Mon, 13 Feb 2017, Julien Grall wrote:
>> Hi Stefano,
>>
>> On 10/02/17 01:01, Stefano Stabellini wrote:
>>> On Fri, 3 Feb 2017, Edgar E. Iglesias wrote:
A possible hack could be to allocate a chunk of DDR dedicated for PCI DMA
On Mon, 13 Feb 2017, Julien Grall wrote:
> Hi Stefano,
>
> On 10/02/17 01:01, Stefano Stabellini wrote:
> > On Fri, 3 Feb 2017, Edgar E. Iglesias wrote:
> > > A possible hack could be to allocate a chunk of DDR dedicated for PCI DMA.
> > > PCI DMA devs could be locked in to only be able to access
Hi Roger,
On 02/02/17 15:40, Roger Pau Monné wrote:
On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall wrote:
Or maybe we could avoid mapping the doorbell in the guest and let Xen
receive an SMMU abort. When receiving the SMMU abort, Xen could sanitize the
value and write into the real MSI
Hi Stefano,
On 10/02/17 01:01, Stefano Stabellini wrote:
On Fri, 3 Feb 2017, Edgar E. Iglesias wrote:
A possible hack could be to allocate a chunk of DDR dedicated for PCI DMA.
PCI DMA devs could be locked in to only be able to access this mem + MSI
doorbell.
Guests can still screw each other
On 02/02/17 15:33, Edgar E. Iglesias wrote:
On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall wrote:
On 31/01/2017 19:06, Edgar E. Iglesias wrote:
On Tue, Jan 31, 2017 at 05:09:53PM +, Julien Grall wrote:
Thank you for the documentation. I am trying to understand if we could move
init
On Fri, 10 Feb 2017, Paul Durrant wrote:
> > -Original Message-
> [snip]
> > > Neither NVIDIA vGPU nor Intel GVT-g are pass-through. They both use
> > emulation to synthesize GPU devices for guests and then use the actual GPU
> > to service the commands sent by the guest driver to the virtu
> -Original Message-
[snip]
> > Neither NVIDIA vGPU nor Intel GVT-g are pass-through. They both use
> emulation to synthesize GPU devices for guests and then use the actual GPU
> to service the commands sent by the guest driver to the virtual GPU. So, I
> think they fall outside the discuss
On Fri, Feb 10, 2017 at 10:11:53AM +, Paul Durrant wrote:
> > -Original Message-
> > From: Roger Pau Monne
> > Sent: 10 February 2017 09:49
> > To: Stefano Stabellini
> > Cc: Julien Grall ; xen-devel > de...@lists.xenproject.org>; Edgar Iglesias (edgar.igles...@xilinx.com)
> > ; Steve
> -Original Message-
> From: Roger Pau Monne
> Sent: 10 February 2017 09:49
> To: Stefano Stabellini
> Cc: Julien Grall ; xen-devel de...@lists.xenproject.org>; Edgar Iglesias (edgar.igles...@xilinx.com)
> ; Steve Capper ; Punit
> Agrawal ; Wei Chen ;
> Campbell Sean ; Shanker Donthineni
On Wed, Feb 01, 2017 at 10:50:49AM -0800, Stefano Stabellini wrote:
> On Wed, 1 Feb 2017, Roger Pau Monné wrote:
> > On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
> > > Hi Stefano,
> > >
> > > On 24/01/17 20:07, Stefano Stabellini wrote:
> > > > On Tue, 24 Jan 2017, Julien Grall wr
On Fri, 3 Feb 2017, Edgar E. Iglesias wrote:
> On Thu, Feb 02, 2017 at 03:12:52PM -0800, Stefano Stabellini wrote:
> > On Thu, 2 Feb 2017, Edgar E. Iglesias wrote:
> > > On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall wrote:
> > > > Hi Edgar,
> > > >
> > > > On 31/01/2017 19:06, Edgar E. Ig
On Thu, Feb 02, 2017 at 03:12:52PM -0800, Stefano Stabellini wrote:
> On Thu, 2 Feb 2017, Edgar E. Iglesias wrote:
> > On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall wrote:
> > > Hi Edgar,
> > >
> > > On 31/01/2017 19:06, Edgar E. Iglesias wrote:
> > > >On Tue, Jan 31, 2017 at 05:09:53PM +
On Thu, 2 Feb 2017, Edgar E. Iglesias wrote:
> On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall wrote:
> > Hi Edgar,
> >
> > On 31/01/2017 19:06, Edgar E. Iglesias wrote:
> > >On Tue, Jan 31, 2017 at 05:09:53PM +, Julien Grall wrote:
> > >>On 31/01/17 16:53, Edgar E. Iglesias wrote:
> >
On Thu, 2 Feb 2017, Julien Grall wrote:
> Hi Roger,
>
> On 01/02/17 10:55, Roger Pau Monné wrote:
> > On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
> > > Hi Stefano,
> > >
> > > On 24/01/17 20:07, Stefano Stabellini wrote:
> > > > On Tue, 24 Jan 2017, Julien Grall wrote:
> > > > >
On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall wrote:
> Or maybe we could avoid mapping the doorbell in the guest and let Xen
> receive an SMMU abort. When receiving the SMMU abort, Xen could sanitize the
> value and write into the real MSI doorbell. Not sure if it would works
> thought.
A
On Wed, Feb 01, 2017 at 07:04:43PM +, Julien Grall wrote:
> Hi Edgar,
>
> On 31/01/2017 19:06, Edgar E. Iglesias wrote:
> >On Tue, Jan 31, 2017 at 05:09:53PM +, Julien Grall wrote:
> >>On 31/01/17 16:53, Edgar E. Iglesias wrote:
> >>>On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall w
Hi Roger,
On 01/02/17 10:55, Roger Pau Monné wrote:
On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
Hi Stefano,
On 24/01/17 20:07, Stefano Stabellini wrote:
On Tue, 24 Jan 2017, Julien Grall wrote:
whilst for Device Tree the segment number is not available.
So Xen needs to rel
Hi Stefano,
On 01/02/2017 19:31, Stefano Stabellini wrote:
On Wed, 1 Feb 2017, Julien Grall wrote:
On 31/01/2017 19:06, Edgar E. Iglesias wrote:
On Tue, Jan 31, 2017 at 05:09:53PM +, Julien Grall wrote:
On 31/01/17 16:53, Edgar E. Iglesias wrote:
On Wed, Jan 25, 2017 at 06:53:20PM +,
Hi Stefano,
On 31/01/2017 21:58, Stefano Stabellini wrote:
On Wed, 25 Jan 2017, Julien Grall wrote:
whilst for Device Tree the segment number is not available.
So Xen needs to rely on DOM0 to discover the host bridges and notify
Xen
with all the relevant informations. This will be done via a n
On Wed, 1 Feb 2017, Julien Grall wrote:
> Hi Edgar,
>
> On 31/01/2017 19:06, Edgar E. Iglesias wrote:
> > On Tue, Jan 31, 2017 at 05:09:53PM +, Julien Grall wrote:
> > > On 31/01/17 16:53, Edgar E. Iglesias wrote:
> > > > On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
> > > > >
Hi Edgar,
On 31/01/2017 19:06, Edgar E. Iglesias wrote:
On Tue, Jan 31, 2017 at 05:09:53PM +, Julien Grall wrote:
On 31/01/17 16:53, Edgar E. Iglesias wrote:
On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
On 24/01/17 20:07, Stefano Stabellini wrote:
On Tue, 24 Jan 2017, Ju
On Wed, 1 Feb 2017, Roger Pau Monné wrote:
> On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
> > Hi Stefano,
> >
> > On 24/01/17 20:07, Stefano Stabellini wrote:
> > > On Tue, 24 Jan 2017, Julien Grall wrote:
> > > > > > whilst for Device Tree the segment number is not available.
> >
On Wed, 1 Feb 2017, Roger Pau Monné wrote:
> On Tue, Jan 31, 2017 at 02:03:16PM -0800, Stefano Stabellini wrote:
> > On Tue, 31 Jan 2017, Julien Grall wrote:
> > > > > > > By default all the PCI devices will be assigned to DOM0. So Xen
> > > > > > > would
> > > > > > > have
> > > > > > > to config
On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
> Hi Stefano,
>
> On 24/01/17 20:07, Stefano Stabellini wrote:
> > On Tue, 24 Jan 2017, Julien Grall wrote:
> > > > > whilst for Device Tree the segment number is not available.
> > > > >
> > > > > So Xen needs to rely on DOM0 to disco
On Tue, Jan 31, 2017 at 02:03:16PM -0800, Stefano Stabellini wrote:
> On Tue, 31 Jan 2017, Julien Grall wrote:
> > > > > > By default all the PCI devices will be assigned to DOM0. So Xen
> > > > > > would
> > > > > > have
> > > > > > to configure the SMMU and Interrupt Controller to allow DOM0 to
On Tue, 31 Jan 2017, Edgar E. Iglesias wrote:
> On Tue, Jan 31, 2017 at 05:09:53PM +, Julien Grall wrote:
> > Hi Edgar,
> >
> > Thank you for the feedbacks.
>
> Hi Julien,
>
> >
> > On 31/01/17 16:53, Edgar E. Iglesias wrote:
> > >On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote
On Tue, 31 Jan 2017, Julien Grall wrote:
> > > > > By default all the PCI devices will be assigned to DOM0. So Xen would
> > > > > have
> > > > > to configure the SMMU and Interrupt Controller to allow DOM0 to use
> > > > > the PCI
> > > > > devices. As mentioned earlier, those subsystems will requ
On Wed, 25 Jan 2017, Julien Grall wrote:
> > > > > whilst for Device Tree the segment number is not available.
> > > > >
> > > > > So Xen needs to rely on DOM0 to discover the host bridges and notify
> > > > > Xen
> > > > > with all the relevant informations. This will be done via a new
> > > > >
On Tue, Jan 31, 2017 at 05:09:53PM +, Julien Grall wrote:
> Hi Edgar,
>
> Thank you for the feedbacks.
Hi Julien,
>
> On 31/01/17 16:53, Edgar E. Iglesias wrote:
> >On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
> >>On 24/01/17 20:07, Stefano Stabellini wrote:
> >>>On Tue, 24
Hi Edgar,
Thank you for the feedbacks.
On 31/01/17 16:53, Edgar E. Iglesias wrote:
On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
On 24/01/17 20:07, Stefano Stabellini wrote:
On Tue, 24 Jan 2017, Julien Grall wrote:
For generic host bridge, the initialization is inexistent. Ho
On Wed, Jan 25, 2017 at 06:53:20PM +, Julien Grall wrote:
> Hi Stefano,
>
> On 24/01/17 20:07, Stefano Stabellini wrote:
> >On Tue, 24 Jan 2017, Julien Grall wrote:
> ## Discovering and register hostbridge
>
> Both ACPI and Device Tree do not provide enough information to fully
>
Hi Roger,
On 25/01/17 11:42, Roger Pau Monné wrote:
On Tue, Jan 24, 2017 at 05:17:06PM +, Julien Grall wrote:
On 06/01/17 15:12, Roger Pau Monné wrote:
On Thu, Dec 29, 2016 at 02:04:15PM +, Julien Grall wrote:
* Add a device
* Remove a device
* Assign a device to a guest
On 30/01/17 07:41, Manish Jaggi wrote:
Hello Julien,
On 01/25/2017 08:55 PM, Julien Grall wrote:
Hello Manish,
On 25/01/17 04:37, Manish Jaggi wrote:
On 01/24/2017 11:13 PM, Julien Grall wrote:
On 19/01/17 05:09, Manish Jaggi wrote:
I think, PCI passthrough and DOM0 w/ACPI enumerating d
Hello Julien,
On 01/25/2017 08:55 PM, Julien Grall wrote:
> Hello Manish,
>
> On 25/01/17 04:37, Manish Jaggi wrote:
>> On 01/24/2017 11:13 PM, Julien Grall wrote:
>>>
>>>
>>> On 19/01/17 05:09, Manish Jaggi wrote:
I think, PCI passthrough and DOM0 w/ACPI enumerating devices on PCI are
Hi Stefano,
On 24/01/17 20:07, Stefano Stabellini wrote:
On Tue, 24 Jan 2017, Julien Grall wrote:
## Discovering and register hostbridge
Both ACPI and Device Tree do not provide enough information to fully
instantiate an host bridge driver. In the case of ACPI, some data may come
from ASL,
T
Hello Manish,
On 25/01/17 04:37, Manish Jaggi wrote:
On 01/24/2017 11:13 PM, Julien Grall wrote:
On 19/01/17 05:09, Manish Jaggi wrote:
I think, PCI passthrough and DOM0 w/ACPI enumerating devices on PCI are
separate features.
Without Xen mapping PCI config space region in stage2 of dom0, A
On Tue, Jan 24, 2017 at 05:17:06PM +, Julien Grall wrote:
> Hi Roger,
>
> On 06/01/17 15:12, Roger Pau Monné wrote:
> > On Thu, Dec 29, 2016 at 02:04:15PM +, Julien Grall wrote:
> > > So given a specific SBDF, it would be possible to find the host bridge
> > > and the
> > > RID associated
On Tue, Jan 24, 2017 at 12:07:16PM -0800, Stefano Stabellini wrote:
> On Tue, 24 Jan 2017, Julien Grall wrote:
> > > > ## Discovering and register hostbridge
> > > >
> > > > Both ACPI and Device Tree do not provide enough information to fully
> > > > instantiate an host bridge driver. In the case
On 01/24/2017 11:13 PM, Julien Grall wrote:
>
>
> On 19/01/17 05:09, Manish Jaggi wrote:
>> Hi Julien,
>
> Hello Manish,
[snip]
>> I think, PCI passthrough and DOM0 w/ACPI enumerating devices on PCI are
>> separate features.
>> Without Xen mapping PCI config space region in stage2 of dom0, A
Hi Julien/Stefano,
On 01/24/2017 07:58 PM, Julien Grall wrote:
> Hi Stefano,
>
> On 04/01/17 00:24, Stefano Stabellini wrote:
>> On Thu, 29 Dec 2016, Julien Grall wrote:
>
> [...]
>
>>> # Introduction
>>>
>>> PCI passthrough allows to give control of physical PCI devices to guest.
>>> This
>>>
On Tue, 24 Jan 2017, Julien Grall wrote:
> > > ## Discovering and register hostbridge
> > >
> > > Both ACPI and Device Tree do not provide enough information to fully
> > > instantiate an host bridge driver. In the case of ACPI, some data may come
> > > from ASL,
> >
> > The data available from A
On 19/01/17 05:09, Manish Jaggi wrote:
Hi Julien,
Hello Manish,
Please trim the quoted e-mail, it is a bit annoying to try to find where
you answer.
On 12/29/2016 07:34 PM, Julien Grall wrote:
DOM0 will issue the hypercall PHYSDEVOP_pci_host_bridge_add for each host
bridge available on
Hi Roger,
On 06/01/17 15:12, Roger Pau Monné wrote:
On Thu, Dec 29, 2016 at 02:04:15PM +, Julien Grall wrote:
Hi all,
The document below is an early version of a design
proposal for PCI Passthrough in Xen. It aims to
describe from an high level perspective the interaction
with the differen
Hi Stefano,
On 04/01/17 00:24, Stefano Stabellini wrote:
On Thu, 29 Dec 2016, Julien Grall wrote:
[...]
# Introduction
PCI passthrough allows to give control of physical PCI devices to guest. This
means that the guest will have full and direct access to the PCI device.
ARM is supporting on
Hi Julien,
On 12/29/2016 07:34 PM, Julien Grall wrote:
> Hi all,
>
> The document below is an early version of a design
> proposal for PCI Passthrough in Xen. It aims to
> describe from an high level perspective the interaction
> with the different subsystems and how guest will be able
> to disco
On Fri, Jan 06, 2017 at 01:12:44PM -0800, Stefano Stabellini wrote:
> On Fri, 6 Jan 2017, Edgar E. Iglesias wrote:
> > On Thu, Dec 29, 2016 at 02:04:15PM +, Julien Grall wrote:
> > > Hi all,
> > >
> > > The document below is an early version of a design
> > > proposal for PCI Passthrough in Xe
On Fri, 6 Jan 2017, Roger Pau Monné wrote:
> > bridge. See [6] for more details.
> >
> > XXX: I think this could be solved by using the host memory layout when
> > creating a guest with PCI devices => Detail it.
>
> I'm not really sure I follow here, but if this write to the MSI doorbell
> doesn'
On Fri, 6 Jan 2017, Edgar E. Iglesias wrote:
> On Thu, Dec 29, 2016 at 02:04:15PM +, Julien Grall wrote:
> > Hi all,
> >
> > The document below is an early version of a design
> > proposal for PCI Passthrough in Xen. It aims to
> > describe from an high level perspective the interaction
> > wi
On Thu, Dec 29, 2016 at 02:04:15PM +, Julien Grall wrote:
> Hi all,
>
> The document below is an early version of a design
> proposal for PCI Passthrough in Xen. It aims to
> describe from an high level perspective the interaction
> with the different subsystems and how guest will be able
> to
On Thu, Dec 29, 2016 at 02:04:15PM +, Julien Grall wrote:
> Hi all,
>
> The document below is an early version of a design
> proposal for PCI Passthrough in Xen. It aims to
> describe from an high level perspective the interaction
> with the different subsystems and how guest will be able
> to
On Thu, 29 Dec 2016, Julien Grall wrote:
> Hi all,
>
> The document below is an early version of a design
> proposal for PCI Passthrough in Xen. It aims to
> describe from an high level perspective the interaction
> with the different subsystems and how guest will be able
> to discover and access
On 29/12/2016 18:41, Jaggi, Manish wrote:
Hi Julien,
Please configure you e-mail client to properly quote a e-mail. The
[manish] solution is hard to read.
*From:* Julien Grall
*Sent:* Thursday, December 29, 2016 10:
Hi Julien,
From: Julien Grall
Sent: Thursday, December 29, 2016 10:33 PM
To: Jaggi, Manish; xen-devel; Stefano Stabellini
Cc: Edgar Iglesias (edgar.igles...@xilinx.com); Steve Capper; Punit Agrawal;
Wei Chen; Campbell Sean; Shanker Donthineni; Jiandi An; Roger Pa
On 29/12/2016 14:16, Jaggi, Manish wrote:
Hi Julien,
Hello Manish,
Wouldnt it be better if the design proposed by cavium be extended by
discussions and comeup with an agreeable to all design.
As I mentioned in my mail, this design is a completely different
approach (emulation vs PV). Th
Hi Julien,
Wouldnt it be better if the design proposed by cavium be extended by
discussions and comeup with an agreeable to all design.
I didnt see any comments on the one I posted.
Putting an altogether new design without commenting on the one posted a month
back, might not be a right approa
Hi all,
The document below is an early version of a design
proposal for PCI Passthrough in Xen. It aims to
describe from an high level perspective the interaction
with the different subsystems and how guest will be able
to discover and access PCI.
I am aware that a similar design has been posted
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