Hi,
On Fri, Sep 22, 2017 at 03:25:00PM -0400, Konrad Rzeszutek Wilk wrote:
> On Fri, Sep 22, 2017 at 09:35:40AM +0200, Sander Eikelenboom wrote:
> > On 22/09/17 04:09, Christopher Clark wrote:
> > > On Thu, Sep 21, 2017 at 1:27 PM, Sander Eikelenboom
> > > wrote:
> > >>
> > >> On Thu, September 2
>>> On 25.09.17 at 18:10, wrote:
> I tried the various device reset patches posted on this discussion
> (do_flr, Christopher's "more thorough" reset_device) but without luck.
>
> After reset, I could notice that lspci shows the device's Masked
> state has been cleared but a newly started guest wi
Hi Jan and al,
- On Sep 21, 2017, at 9:12 AM, Jan Beulich jbeul...@suse.com wrote:
> And did you verify that the OS actually makes an attempt to clear
> this mask-all flag? If such an attempt doesn't have the intended
> effect, finding the problem location in the code and sending a
> fix can'
>
> [snip]
>
>
> > So i think David's NACK was mostly for the patchset having some hackish
> cosmetics.
>
> He didn't like 'do_flr' which made sense as the patchset did not do FLR.
> It made a bus-reset
> for more than one device (if those devices were assigned to pciback).
>
When I first wrote
On Fri, Sep 22, 2017 at 09:35:40AM +0200, Sander Eikelenboom wrote:
> - Not an issue back then when the patch was made, but as the question earlier
> to Roger,
> the hypervisor seems to grow more interference with pci devices with the
> PVH dom0 work.
> If and hoow does that relate to pci-bac
On Fri, Sep 22, 2017 at 09:35:40AM +0200, Sander Eikelenboom wrote:
> On 22/09/17 04:09, Christopher Clark wrote:
> > On Thu, Sep 21, 2017 at 1:27 PM, Sander Eikelenboom
> > wrote:
> >>
> >> On Thu, September 21, 2017, 10:39:52 AM, Roger Pau Monné wrote:
> >>
> >>> On Wed, Sep 20, 2017 at 03:50:35
On Thu, Sep 21, 2017 at 10:27:01PM +0200, Sander Eikelenboom wrote:
> Roger:
> I follow your PVH (dom0) patches shallowly, from my understanding it will
> result
> in Xen having more inteference with the handling of PCI devices ?
Yes, that's correct.
> If that's correct will this also impact t
On 22/09/17 04:09, Christopher Clark wrote:
> On Thu, Sep 21, 2017 at 1:27 PM, Sander Eikelenboom
> wrote:
>>
>> On Thu, September 21, 2017, 10:39:52 AM, Roger Pau Monné wrote:
>>
>>> On Wed, Sep 20, 2017 at 03:50:35PM -0400, Jérôme Oufella wrote:
I'm using PCI pass-through to map a PCIe
Hi,
On Thu, Sep 21, 2017 at 07:09:12PM -0700, Christopher Clark wrote:
> On Thu, Sep 21, 2017 at 1:27 PM, Sander Eikelenboom
> wrote:
> >
> > On Thu, September 21, 2017, 10:39:52 AM, Roger Pau Monné wrote:
> >
> >> On Wed, Sep 20, 2017 at 03:50:35PM -0400, Jérôme Oufella wrote:
> >>>
> >>> I'm us
On Thu, Sep 21, 2017 at 1:27 PM, Sander Eikelenboom
wrote:
>
> On Thu, September 21, 2017, 10:39:52 AM, Roger Pau Monné wrote:
>
>> On Wed, Sep 20, 2017 at 03:50:35PM -0400, Jérôme Oufella wrote:
>>>
>>> I'm using PCI pass-through to map a PCIe (intel i210) controller into
>>> a HVM domain. The sy
Thursday, September 21, 2017, 10:39:52 AM, you wrote:
> On Wed, Sep 20, 2017 at 03:50:35PM -0400, Jérôme Oufella wrote:
>> Hi Xen-devel,
>>
>> I'm using PCI pass-through to map a PCIe (intel i210) controller into
>> a HVM domain. The system uses xen-pciback to hide the appropriate PCI
>> devi
>>> On 20.09.17 at 21:50, wrote:
> - On Dom0, 'lspci -vv' on that PCIe device between the "working" and
> the "muted interrupts" states, I noted a difference between the
> MSI-X caps:
>
> - Capabilities: [70] MSI-X: Enable- Count=5 Masked- <-- IRQs will work if
> domain started
> + Capabilit
On Wed, Sep 20, 2017 at 03:50:35PM -0400, Jérôme Oufella wrote:
> Hi Xen-devel,
>
> I'm using PCI pass-through to map a PCIe (intel i210) controller into
> a HVM domain. The system uses xen-pciback to hide the appropriate PCI
> device from Dom0.
>
> When creating the HVM domain after an hyper
Hi Xen-devel,
I'm using PCI pass-through to map a PCIe (intel i210) controller into
a HVM domain. The system uses xen-pciback to hide the appropriate PCI
device from Dom0.
When creating the HVM domain after an hypervisor cold boot, the HVM
domain can access and use the PCIe controller withou
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