>>> On 16.09.15 at 22:31, wrote:
> I think the lspci -v output is the same in both cases with the exception
> of the xhci_pci which is not present in the Native case lspci -v output.
> xhci_pci is built into the kernel. The same kernel/system is used with
> this system when booted with Dom0 and na
On Fri, 2015-09-11 at 04:03 -0600, Jan Beulich wrote:
> >>> On 10.09.15 at 18:20, wrote:
> > On Wed, 2015-09-09 at 00:48 -0600, Jan Beulich wrote:
> >> >>> On 08.09.15 at 18:02, wrote:
> >> > I believe the driver does support use of multiple interrupts based on
> >> > the previous explanation
>>> On 10.09.15 at 18:20, wrote:
> On Wed, 2015-09-09 at 00:48 -0600, Jan Beulich wrote:
>> >>> On 08.09.15 at 18:02, wrote:
>> > I believe the driver does support use of multiple interrupts based on
>> > the previous explanation of the lspci output where it was established
>> > that the device c
>>> On 08.09.15 at 18:02, wrote:
> I believe the driver does support use of multiple interrupts based on
> the previous explanation of the lspci output where it was established
> that the device could use up to 8 interrupts which is what I see on bare
> metal.
Where is the proof of that? All I've
>>> On 03.09.15 at 18:52, wrote:
> On Thu, 2015-09-03 at 09:04 -0600, Jan Beulich wrote:
>> >>> On 03.09.15 at 14:04, wrote:
>> > I am still confused as to whether any device, or in this case
>> > xhci_hcd,
>> > can use more than one cpu at any given time. My understanding based on
>>
>>> On 03.09.15 at 14:04, wrote:
On 02.09.15 at 19:17, wrote:
>> From: Jan Beulich
>> Sent: Wednesday, September 2, 2015 4:58 AM
> Justin Acker 09/02/15 1:14 AM >>>
>>> 00:14.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset
> Family USB xHCI Host Controller (rev
(re-adding xen-devel)
>>> On 02.09.15 at 19:17, wrote:
> From: Jan Beulich
> Sent: Wednesday, September 2, 2015 4:58 AM
Justin Acker 09/02/15 1:14 AM >>>
>> 00:14.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset
>> Family USB xHCI Host Controller (rev 04) (prog-if 3
l] xhci_hcd intterrupt affinity in Dom0/DomU
> limited to single interrupt
>
> On 01/09/15 18:39, Justin Acker wrote:
>
>
>
>> Taking this to the dev list from users.
>>
>> Is there a way to force or enable pirq delivery to a set of cpus as
>>
From: Ian Campbell
To: Konrad Rzeszutek Wilk ; Justin Acker
Cc: "boris.ostrov...@oracle.com" ;
"xen-devel@lists.xen.org"
Sent: Wednesday, September 2, 2015 9:49 AM
Subject: Re: [Xen-devel] xhci_hcd intterrupt affinity in Dom0/DomU limited to
single interrupt
From: Konrad Rzeszutek Wilk
To: Justin Acker
Cc: "xen-devel@lists.xen.org" ;
"boris.ostrov...@oracle.com"
Sent: Wednesday, September 2, 2015 8:53 AM
Subject: Re: [Xen-devel] xhci_hcd intterrupt affinity in Dom0/DomU limited to
single interrupt
On Tue, S
oracle.com
> > Sent: Tuesday, September 1, 2015 4:56 PM
> > Subject: Re: [Xen-devel] xhci_hcd intterrupt affinity in Dom0/DomU
> > limited to single interrupt
> >
> > On Tue, Sep 01, 2015 at 05:39:46PM +, Justin Acker wrote:
> > > Taking this to the
On 01/09/15 18:39, Justin Acker wrote:
> Taking this to the dev list from users.
>
> Is there a way to force or enable pirq delivery to a set of cpus as
> opposed to single device from being a assigned a single pirq so that its
> interrupt can be distributed across multiple cpus?
No.
PIRQs are d
On Tue, Sep 01, 2015 at 11:09:38PM +, Justin Acker wrote:
>
> From: Konrad Rzeszutek Wilk
> To: Justin Acker
> Cc: "xen-devel@lists.xen.org" ;
> boris.ostrov...@oracle.com
> Sent: Tuesday, September 1, 2015 4:56 PM
> Subject: Re: [Xen-devel] xhci_
On 09/01/2015 04:56 PM, Konrad Rzeszutek Wilk wrote:
On Tue, Sep 01, 2015 at 05:39:46PM +, Justin Acker wrote:
Taking this to the dev list from users.
Is there a way to force or enable pirq delivery to a set of cpus as opposed to
single device from being a assigned a single pirq so that it
On Tue, Sep 01, 2015 at 05:39:46PM +, Justin Acker wrote:
> Taking this to the dev list from users.
>
> Is there a way to force or enable pirq delivery to a set of cpus as opposed
> to single device from being a assigned a single pirq so that its interrupt
> can be distributed across multip
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