flight 183369 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183369/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stopfail like 183365
test-amd64-amd64-xl-qemuu-win7-amd64
flight 183370 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183370/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-libvirt 15 migrate-support-checkfail never pass
test-arm64-arm64-xl-xsm 1
flight 183367 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183367/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stop fail blocked in 183363
test-armhf-armhf-libvirt 16 save
Hi Julien,
(Sending this email directly “To:” Bertrand and Stefano to catch their
attention about
one question that you ask them)
> On Oct 14, 2023, at 02:31, Julien Grall wrote:
>
> Hi Henry,
>
> some more remarks.
>
> On 09/10/2023 02:03, Henry Wang wrote:
>> +/*
>> + * Invalidate all entr
Hi Julien,
> On Oct 14, 2023, at 02:22, Julien Grall wrote:
>
> Hi Henry,
>
> On 09/10/2023 02:03, Henry Wang wrote:
>> From: Penny Zheng
>> Current P2M implementation is designed for MMU system only.
>> We move the MMU-specific codes into mmu/p2m.c, and only keep generic
>> codes in p2m.c, li
Hi Julien,
> On Oct 14, 2023, at 01:48, Julien Grall wrote:
>
> On 13/10/2023 18:47, Julien Grall wrote:
>> Hi Henry,
>> On 09/10/2023 02:03, Henry Wang wrote:
>>> From: Penny Zheng
>>>
>>> init_secondary_pagetables() is a function in the common code path
>>> of both MMU and future MPU support
Hi Julien,
> On Oct 14, 2023, at 01:44, Julien Grall wrote:
>
> Hi Henry,
>
> On 09/10/2023 02:03, Henry Wang wrote:
>> diff --git a/xen/arch/arm/mmu/setup.c b/xen/arch/arm/mmu/setup.c
>> index c2df976ab2..dff81f6125 100644
>> --- a/xen/arch/arm/mmu/setup.c
>> +++ b/xen/arch/arm/mmu/setup.c
>>
Hi Julien,
> On Oct 14, 2023, at 01:40, Julien Grall wrote:
>
> Hi Henry,
>
> On 09/10/2023 02:03, Henry Wang wrote:
>> setup_mm() is used for Xen to setup memory management subsystem,
>> such as boot allocator, direct-mapping, xenheap initialization,
>> frametable and static memory pages, at b
Hi Julien,
> On Oct 14, 2023, at 01:26, Julien Grall wrote:
>
> Hi Henry,
>
> On 09/10/2023 02:03, Henry Wang wrote:
>> Currently mmu_init_secondary_cpu() only enforces the page table
>> should not contain mapping that are both Writable and eXecutables
>> after boot. To ease the arch/arm/mm.c s
Hi Julien,
> On Oct 14, 2023, at 01:16, Julien Grall wrote:
>
> Hi Henry,
>
> On 09/10/2023 02:03, Henry Wang wrote:
>> +#ifdef CONFIG_ARM_64
>> +int init_secondary_pagetables(int cpu)
>> +{
>> +clear_boot_pagetables();
>> +
>> +/*
>> + * Set init_ttbr for this CPU coming up. All CP
On Fri, 13 Oct 2023, Stefano Stabellini wrote:
> On Fri, 13 Oct 2023, Federico Serafini wrote:
> > Add missing parameter names, no functional change.
> >
> > Signed-off-by: Federico Serafini
> > ---
> > xen/arch/arm/include/asm/cpufeature.h | 8
> > 1 file changed, 4 insertions(+), 4 de
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter names, no functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter names, no funtional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter name, no functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter name, no functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter names, no functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter name, no functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter names, no functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter name, no functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter names, no functional change.
>
> Signed-off-by: Federico Serafini
> ---
> xen/arch/arm/include/asm/cpufeature.h | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/xen/arch/arm/include/asm/cpufeat
On Fri, 13 Oct 2023, Federico Serafini wrote:
> Add missing parameter names, no functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
On Fri, 13 Oct 2023, Julien Grall wrote:
> Hi George,
>
> On 13/10/2023 17:06, George Dunlap wrote:
> > On Fri, Oct 13, 2023 at 4:56 PM Julien Grall wrote:
> > > > The initial patch that
> > > > introduced it didn't mention wanting to include dom0 specifically; on
> > > > the contrary it said:
>
From: George Dunlap
Commit fc2b57c9a ("xenstored: send an evtchn notification on
introduce_domain") introduced the sending of an event channel to the
guest when first introduced, so that dom0less domains waiting for the
connection would know that xenstore was ready to use.
Unfortunately, it was
On Fri, 13 Oct 2023, Nicola Vetrini wrote:
> This file contains the deviation that are not marked by
> a deviation comment, as specified in
> docs/misra/documenting-violations.rst.
>
> Signed-off-by: Nicola Vetrini
> Release-acked-by: Henry Wang
Reviewed-by: Stefano Stabellini
Volodymyr Babchuk writes:
> From: Oleksandr Andrushchenko
>
> Xen and/or Dom0 may have put values in PCI_COMMAND which they expect
> to remain unaltered. PCI_COMMAND_SERR bit is a good example: while the
> guest's view of this will want to be zero initially, the host having set
> it to 1 may n
On Thu, Oct 12, 2023 at 12:25 AM Heiko Carstens wrote:
>
> On Mon, Aug 07, 2023 at 04:04:56PM -0700, Vishal Moola (Oracle) wrote:
> > As part of the conversions to replace pgtable constructor/destructors with
> > ptdesc equivalents, convert various page table functions to use ptdescs.
> >
> > Some
flight 183365 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183365/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stopfail like 183362
test-amd64-amd64-xl-qemuu-win7-amd64
Hi Xen developers list,
TL;DR:
--
Causing certain web server traffic on a secondary VLAN on Raspberry Pi
under vanilla Debian/UEFI in combination with Xen leads to complete
system reboot (watchdog triggering for Dom0). Other strange things are
happening.
Description:
--
I recen
Hi Henry,
some more remarks.
On 09/10/2023 02:03, Henry Wang wrote:
+/*
+ * Invalidate all entries in the root page-tables. This is
+ * useful to get fault on entry and do an action.
+ *
+ * p2m_invalid_root() should not be called when the P2M is shared with
+ * the IOMMU because it will cause
Hi Henry,
On 09/10/2023 02:03, Henry Wang wrote:
From: Penny Zheng
Current P2M implementation is designed for MMU system only.
We move the MMU-specific codes into mmu/p2m.c, and only keep generic
codes in p2m.c, like VMID allocator, etc. We also move MMU-specific
definitions and declarations t
Thanks for taking a look, Michal.
On Fri, Oct 13, 2023 at 12:17 PM Wilczynski, Michal
wrote:
>
> Hi,
>
> On 10/10/2023 7:39 PM, Jason Andryuk wrote:
> > From: Roger Pau Monne
> >
> > The Processor capability bits notify ACPI of the OS capabilities, and
> > so ACPI can adjust the return of other
Implement a basic exception handler that dumps the CPU state to the
console, as well as the code required to set the correct exception
vector table's base address in setup.c.
Signed-off-by: Shawn Anastasio
---
v2:
- Place {h_,}exception_common in .text.exceptions section
- Use assembler macro
On Power, the exception vectors must lie at a fixed address, depending
on the state of the Alternate Interrupt Location (AIL) field of the
Logical Partition Control Register (LPCR). Create a .text.exceptions
section in the linker script at an address suitable for AIL=3 plus an
accompanying assertio
Hello all,
This series implements a basic exception handler and the required
support infrastructure on Power. Currently the handler just dumps all
registers to the serial console and nothing else, but even this is
useful for debugging during early bring-up.
Thanks,
Shawn Anastasio (2):
xen/ppc
Hi Stewart,
Stewart Hildebrand writes:
> On 10/12/23 18:09, Volodymyr Babchuk wrote:
>> This function can be used when user wants to remove all rangeset
>> entries but do not want to destroy rangeset itself.
>>
>> Signed-off-by: Volodymyr Babchuk
>>
>> ---
>>
>> Changes in v10:
>>
>> - N
On 9/29/23 4:48 AM, Andrew Cooper wrote:
> On 29/09/2023 12:19 am, Shawn Anastasio wrote:
>> Implement a basic exception handler that dumps the CPU state to the
>> console, as well as the code required to set the correct exception
>> vector table's base address in setup.c.
>>
>> Signed-off-by: Shaw
On 10/12/23 18:09, Volodymyr Babchuk wrote:
> This function can be used when user wants to remove all rangeset
> entries but do not want to destroy rangeset itself.
>
> Signed-off-by: Volodymyr Babchuk
>
> ---
>
> Changes in v10:
>
> - New in v10. The function is used in "vpci/header: handle
On 13/10/2023 18:47, Julien Grall wrote:
Hi Henry,
On 09/10/2023 02:03, Henry Wang wrote:
From: Penny Zheng
init_secondary_pagetables() is a function in the common code path
of both MMU and future MPU support. Since "page table" is a MMU
specific concept, rename init_secondary_pagetables()
Hi Henry,
On 09/10/2023 02:03, Henry Wang wrote:
From: Penny Zheng
init_secondary_pagetables() is a function in the common code path
of both MMU and future MPU support. Since "page table" is a MMU
specific concept, rename init_secondary_pagetables() to a generic
name prepare_secondary_mm() as
Hi Henry,
On 09/10/2023 02:03, Henry Wang wrote:
diff --git a/xen/arch/arm/mmu/setup.c b/xen/arch/arm/mmu/setup.c
index c2df976ab2..dff81f6125 100644
--- a/xen/arch/arm/mmu/setup.c
+++ b/xen/arch/arm/mmu/setup.c
@@ -339,6 +339,33 @@ void free_init_memory(void)
printk("Freed %ldkB init memo
Hi Henry,
On 09/10/2023 02:03, Henry Wang wrote:
setup_mm() is used for Xen to setup memory management subsystem,
such as boot allocator, direct-mapping, xenheap initialization,
frametable and static memory pages, at boot time.
We could inherit some components seamlessly for MPU support, such
a
Hi Henry,
On 09/10/2023 02:03, Henry Wang wrote:
Currently, most of the code is in arm/mm.{c,h} and arm/arm64/mm.c
is MMU-specific. To make the MM code extendable, this commit extracts
the MMU-specific MM code.
Extract the boot CPU MM bringup code from arm/mm.c to mmu/setup.c.
While moving, mar
Hi Henry,
On 09/10/2023 02:03, Henry Wang wrote:
Currently mmu_init_secondary_cpu() only enforces the page table
should not contain mapping that are both Writable and eXecutables
after boot. To ease the arch/arm/mm.c split work, fold this function
to head.S.
Introduce assembly macro pt_enforce_
Julien,
Julien Grall writes:
> Hi,
>
> On 13/10/2023 14:06, Volodymyr Babchuk wrote:
>> Hi Julien,
>> Julien Grall writes:
>>
>>> Hi Volodymyr,
>>>
>>> On 12/10/2023 23:09, Volodymyr Babchuk wrote:
From: Oleksandr Andrushchenko
At the moment, we always allocate an extra 16 slots f
Hi Henry,
On 09/10/2023 02:03, Henry Wang wrote:
+#ifdef CONFIG_ARM_64
+int init_secondary_pagetables(int cpu)
+{
+clear_boot_pagetables();
+
+/*
+ * Set init_ttbr for this CPU coming up. All CPus share a single setof
+ * pagetables, but rewrite it each time for consistency with
Hi,
On 13/10/2023 14:06, Volodymyr Babchuk wrote:
Hi Julien,
Julien Grall writes:
Hi Volodymyr,
On 12/10/2023 23:09, Volodymyr Babchuk wrote:
From: Oleksandr Andrushchenko
At the moment, we always allocate an extra 16 slots for IO handlers
(see MAX_IO_HANDLER). So while adding IO trap ha
Hi,
On 10/10/2023 7:39 PM, Jason Andryuk wrote:
> From: Roger Pau Monne
>
> The Processor capability bits notify ACPI of the OS capabilities, and
> so ACPI can adjust the return of other Processor methods taking the OS
> capabilities into account.
>
> When Linux is running as a Xen dom0, the hype
Hi George,
On 13/10/2023 17:06, George Dunlap wrote:
On Fri, Oct 13, 2023 at 4:56 PM Julien Grall wrote:
The initial patch that
introduced it didn't mention wanting to include dom0 specifically; on
the contrary it said:
"The extra notification is harmless for domains that don't require it."
On Fri, Oct 13, 2023 at 4:56 PM Julien Grall wrote:
> > The initial patch that
> > introduced it didn't mention wanting to include dom0 specifically; on
> > the contrary it said:
> >
> > "The extra notification is harmless for domains that don't require it."
>
> ... even if this is what the commit
On 13/10/2023 14:30, George Dunlap wrote:
On Fri, Oct 13, 2023 at 2:00 PM Julien Grall wrote:
If the problem is the delay between the xenevtchn_notify() in
introduce_domain() and the domain_conn_reset() afterwards in
do_domain(), would it make sense instead to move the notification into
do_i
Fix adapted off Linux's mailing list:
https://lore.kernel.org/lkml/d99589f4-bc5d-430b-87b2-72c20370c...@exactcode.com/T/#u
Signed-off-by: Alejandro Vallejo
Release-acked-by: Henry Wang
---
v3:
* Factored MSR shuffling into a separate function and moved the call to
the end of init_amd()
On 13.10.23 17:16, George Dunlap wrote:
On Fri, Oct 13, 2023 at 4:04 PM Juergen Gross wrote:
Technically, dom0 has exactly the same problem as dom0less domains it boots
before Xenstored is running and therefore it may need to know when it is
ready to receive commands.
Umm, no, not really.
Th
On 13/10/2023 16:04, Juergen Gross wrote:
On 13.10.23 16:51, Julien Grall wrote:
A dom0less domU doesn't have that negotiation with xenstored, as
xenstored just
uses the pre-defined grant for looking at the ring page. For the domU
there is
no way to tell that xenstored has initialized the ri
Add missing parameter names, no functional change.
Signed-off-by: Federico Serafini
---
xen/drivers/passthrough/arm/smmu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/xen/drivers/passthrough/arm/smmu.c
b/xen/drivers/passthrough/arm/smmu.c
index 71799064f8..11fc1d22
Add missing parameter names, no funtional change.
Signed-off-by: Federico Serafini
---
xen/arch/arm/include/asm/domain.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/include/asm/domain.h
b/xen/arch/arm/include/asm/domain.h
index 99e798..5fb8cd79c0 100
This patch series addresses some of the violations of Rule 8.2 adding the
missing parameter names.
Federico Serafini (10):
arm/gic: address violations of MISRA C:2012 Rule 8.2
arm/cpufeature: address violations of MISRA C:2012 Rule 8.2
arm/smpboot: address violations of MISRA C:2012 Rule 8.2
Add missing parameter names, no functional change.
Signed-off-by: Federico Serafini
---
xen/arch/arm/include/asm/setup.h | 5 +++--
xen/arch/arm/setup.c | 4 ++--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/include/asm/setup.h b/xen/arch/arm/include/as
Add missing parameter names, no functional change.
Signed-off-by: Federico Serafini
---
xen/arch/arm/include/asm/arm32/cmpxchg.h | 2 +-
xen/arch/arm/include/asm/arm64/cmpxchg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/include/asm/arm32/cmpxchg.h
b/xen
Add missing parameter names, no functional change.
Signed-off-by: Federico Serafini
---
xen/arch/arm/include/asm/cpufeature.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/include/asm/cpufeature.h
b/xen/arch/arm/include/asm/cpufeature.h
index 8011076b8
Add missing parameter name, no functional change.
Signed-off-by: Federico Serafini
---
xen/arch/arm/vgic-v3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 05a009409a..cc38327701 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b
Add missing parameter name, no functional change.
Signed-off-by: Federico Serafini
---
xen/arch/arm/traps.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index ce89f16404..5aa14d4707 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arc
Add missing parameter name, no functional change.
Signed-off-by: Federico Serafini
---
xen/arch/arm/include/asm/p2m.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h
index 940495d42b..9ad312bfb5 100644
--- a/xen/
Add missing parameter name, no functional change.
Signed-off-by: Federico Serafini
---
xen/arch/arm/arm64/smpboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/arm/arm64/smpboot.c b/xen/arch/arm/arm64/smpboot.c
index 9637f42469..bf81d018b3 100644
--- a/xen/arch/a
Add missing parameter names, no functional change.
Signed-off-by: Federico Serafini
---
xen/arch/arm/include/asm/gic.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h
index f1ef347edc..03f209529b 100
On Fri, Oct 13, 2023 at 4:04 PM Juergen Gross wrote:
> >>> Technically, dom0 has exactly the same problem as dom0less domains it
> >>> boots
> >>> before Xenstored is running and therefore it may need to know when it is
> >>> ready to receive commands.
> >>
> >> Umm, no, not really.
> >>
> >> The
On 13/10/2023 11:27, Julien Grall wrote:
Hi Andrew,
On 11/10/2023 08:51, Andrew Cooper wrote:
On 11/10/2023 3:47 pm, Nicola Vetrini wrote:
On 11/10/2023 02:15, Andrew Cooper wrote:
On 10/10/2023 5:31 pm, Nicola Vetrini wrote:
Hi,
as you can see from [1], there's a MISRA C guideline, D4.11,
On 13.10.23 16:51, Julien Grall wrote:
Hi Juergen,
On 13/10/2023 15:47, Juergen Gross wrote:
On 13.10.23 13:22, Julien Grall wrote:
Hi George,
On 13/10/2023 11:16, George Dunlap wrote:
On Thu, Oct 12, 2023 at 11:36 PM Stefano Stabellini
wrote:
On Thu, 12 Oct 2023, George Dunlap wrote:
St
On 13/10/2023 10:33 pm, Alejandro Vallejo wrote:
> On Fri, Oct 13, 2023 at 09:40:52PM +0800, Andrew Cooper wrote:
>> On 13/10/2023 9:18 pm, Alejandro Vallejo wrote:
>> This will surely be a core scope MSR rather than thread scope,
> It is, though I doubt it matters a whole lot. The writes are consi
Hi,
On Fri, Oct 13, 2023 at 03:41:49PM +0100, Julien Grall wrote:
> Hi Alejandro,
>
> The original e-mail didn't yet reach my inbox. So answering here as there
> are enough context.
>
> On 13/10/2023 15:33, Alejandro Vallejo wrote:
> > On Fri, Oct 13, 2023 at 09:40:52PM +0800, Andrew Cooper wrot
Hi Juergen,
On 13/10/2023 15:47, Juergen Gross wrote:
On 13.10.23 13:22, Julien Grall wrote:
Hi George,
On 13/10/2023 11:16, George Dunlap wrote:
On Thu, Oct 12, 2023 at 11:36 PM Stefano Stabellini
wrote:
On Thu, 12 Oct 2023, George Dunlap wrote:
Stop tinkering in the hope that it hides t
On 13.10.23 13:22, Julien Grall wrote:
Hi George,
On 13/10/2023 11:16, George Dunlap wrote:
On Thu, Oct 12, 2023 at 11:36 PM Stefano Stabellini
wrote:
On Thu, 12 Oct 2023, George Dunlap wrote:
Stop tinkering in the hope that it hides the problem. You're only
making it harder to fix properl
Hi Alejandro,
The original e-mail didn't yet reach my inbox. So answering here as
there are enough context.
On 13/10/2023 15:33, Alejandro Vallejo wrote:
On Fri, Oct 13, 2023 at 09:40:52PM +0800, Andrew Cooper wrote:
On 13/10/2023 9:18 pm, Alejandro Vallejo wrote:
diff --git a/xen/arch/x86/
On Fri, Oct 13, 2023 at 09:40:52PM +0800, Andrew Cooper wrote:
> On 13/10/2023 9:18 pm, Alejandro Vallejo wrote:
> > diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
> > index 4f27187f92..085c4772d7 100644
> > --- a/xen/arch/x86/cpu/amd.c
> > +++ b/xen/arch/x86/cpu/amd.c
> > @@ -1167,6
On 13/10/2023 7:36 pm, Roger Pau Monné wrote:
> On Fri, Oct 13, 2023 at 12:23:43PM +0100, Alejandro Vallejo wrote:
diff --git a/xen/arch/x86/include/asm/amd.h
b/xen/arch/x86/include/asm/amd.h
index d862cb7972..5a40bcc2ba 100644
--- a/xen/arch/x86/include/asm/amd.h
+++ b/xe
On 13/10/2023 9:18 pm, Alejandro Vallejo wrote:
> diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
> index 4f27187f92..085c4772d7 100644
> --- a/xen/arch/x86/cpu/amd.c
> +++ b/xen/arch/x86/cpu/amd.c
> @@ -1167,6 +1167,14 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
> if
On Fri, Oct 13, 2023 at 2:00 PM Julien Grall wrote:
> >>> If the problem is the delay between the xenevtchn_notify() in
> >>> introduce_domain() and the domain_conn_reset() afterwards in
> >>> do_domain(), would it make sense instead to move the notification into
> >>> do_introduce(), after the do
Fix adapted off Linux's mailing list:
https://lore.kernel.org/lkml/d99589f4-bc5d-430b-87b2-72c20370c...@exactcode.com/T/#u
Signed-off-by: Alejandro Vallejo
Release-acked-by: Henry Wang
---
v2:
* Removed v1/patch1, as it proved to be contentious
* Also changed is_zen[34]_uarch() into a h
flight 183363 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183363/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-arm64 6 xen-buildfail REGR. vs. 183360
Tests which are fa
Hi Julien,
Julien Grall writes:
> Hi Volodymyr,
>
> On 12/10/2023 23:09, Volodymyr Babchuk wrote:
>> From: Oleksandr Andrushchenko
>> At the moment, we always allocate an extra 16 slots for IO handlers
>> (see MAX_IO_HANDLER). So while adding IO trap handlers for the emulated
>> MSI-X registe
Hi George,
On 13/10/2023 12:32, George Dunlap wrote:
On Fri, Oct 13, 2023 at 12:22 PM Julien Grall wrote:
On 13/10/2023 11:16, George Dunlap wrote:
On Thu, Oct 12, 2023 at 11:36 PM Stefano Stabellini
wrote:
On Thu, 12 Oct 2023, George Dunlap wrote:
Stop tinkering in the hope that it hides
flight 183362 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183362/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stopfail like 183359
test-amd64-amd64-xl-qemuu-win7-amd64
On ADLink AVA platform (Ampere Altra SoC with 32 Arm Neoverse N1 cores),
the physical memory regions are:
DRAM memory regions:
Node[0] Region[0]: 0x8000 - 0x
Node[0] Region[1]: 0x0800 - 0x08007fff
Node[0] Region[2]: 0x0801 - 0x0807
The
The latest Xen fails to boot on ADLink AVA platform. Alexey Klimov root
caused the issue is related with the commit 1c78d76b67 ("xen/arm64: mm:
Introduce helpers to prepare/enable/disable").
This is because on ADLink AVA platform, it loads Xen hypervisor to the
address above 8TB and hence causes
Xen maps the virtual memory space starting from L0 slot 4, so it's open
coded for macros with the offset '4'.
For more readable, add a new macro XEN_VM_MAPPING which defines the
start slot for Xen virtual memory mapping, and all virtual memory
regions are defined based on it.
Acked-by: Julien Gra
Currently, Xen doesn't check the status property of memory/reserved
memory nodes, which may lead to the following issues:
- If a memory node has a status "disabled" it implies that it should
not be used. Xen does not handle the status property for the memory
node and ends up using it.
- If a
Hi Michal,
On Fri, Oct 13, 2023 at 01:00:12PM +0200, Michal Orzel wrote:
> Hi Leo,
>
> On 13/10/2023 12:29, Leo Yan wrote:
> >
> >
> > Currently, the Xen hypervisor doesn't handle the status, the issue can
> > be described from two perspectives: the memory nodes and the reserved
> > memory node
flight 183364 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183364/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-libvirt 15 migrate-support-checkfail never pass
test-arm64-arm64-xl-xsm 1
On Fri, Oct 13, 2023 at 12:23:43PM +0100, Alejandro Vallejo wrote:
> Hi,
>
> I'll just remove this patch (and amend the next) in the interest of having
> it committed early. That said...
>
> On Fri, Oct 13, 2023 at 10:14:45AM +0800, Andrew Cooper wrote:
> > On 13/10/2023 1:26 am, Alejandro Vallej
On Fri, Oct 13, 2023 at 12:22 PM Julien Grall wrote:
>
> Hi George,
>
> On 13/10/2023 11:16, George Dunlap wrote:
> > On Thu, Oct 12, 2023 at 11:36 PM Stefano Stabellini
> > wrote:
> >>
> >> On Thu, 12 Oct 2023, George Dunlap wrote:
> > Stop tinkering in the hope that it hides the problem. Y
Hi,
I'll just remove this patch (and amend the next) in the interest of having
it committed early. That said...
On Fri, Oct 13, 2023 at 10:14:45AM +0800, Andrew Cooper wrote:
> On 13/10/2023 1:26 am, Alejandro Vallejo wrote:
> > It slightly simplifies the code that uses them at no real cost becau
Hi George,
On 13/10/2023 11:16, George Dunlap wrote:
On Thu, Oct 12, 2023 at 11:36 PM Stefano Stabellini
wrote:
On Thu, 12 Oct 2023, George Dunlap wrote:
Stop tinkering in the hope that it hides the problem. You're only
making it harder to fix properly.
Making it harder to fix properly wo
Hi,
On 13/10/2023 07:31, Juergen Gross wrote:
On 13.10.23 00:36, Stefano Stabellini wrote:
On Thu, 12 Oct 2023, George Dunlap wrote:
Stop tinkering in the hope that it hides the problem. You're only
making it harder to fix properly.
Making it harder to fix properly would be a valid reason n
Hi Leo,
On 13/10/2023 12:29, Leo Yan wrote:
>
>
> Currently, the Xen hypervisor doesn't handle the status, the issue can
> be described from two perspectives: the memory nodes and the reserved
> memory nodes.
The first part about the status is a bit ambiguous.
How about (this can be done on comm
Allow 16 bits per cpu number, which is the limit imposed by
spinlock_tickets_t.
This will allow up to 65535 cpus, while increasing only the size of
recursive spinlocks in debug builds from 8 to 12 bytes.
Signed-off-by: Juergen Gross
---
xen/common/spinlock.c | 1 +
xen/include/xen/spinloc
In reality all spin_*() functions are macros which are defined to just
call a related real function.
Remove this macro layer, as it is adding complexity without any gain.
Signed-off-by: Juergen Gross
---
V2:
- new patch
---
xen/common/spinlock.c | 28 +-
xen/include/xen/spi
On 13/10/2023 10:25, Julien Grall wrote:
Hi Nicola,
On 12/10/2023 16:28, Nicola Vetrini wrote:
The purpose of this macro is to encapsulate the well-known expression
'x & -x', that in 2's complement architectures on unsigned integers
will
give 2^ffs(x), where ffs(x) is the position of the lowes
On 13/10/2023 01:31, Stefano Stabellini wrote:
On Thu, 12 Oct 2023, Nicola Vetrini wrote:
The purpose of this macro is to encapsulate the well-known expression
'x & -x', that in 2's complement architectures on unsigned integers
will
give 2^ffs(x), where ffs(x) is the position of the lowest set
Recursive and normal spinlocks are sharing the same data structure for
representation of the lock. This has two major disadvantages:
- it is not clear from the definition of a lock, whether it is intended
to be used recursive or not, while a mixture of both usage variants
needs to be
- in pro
Struct lock_profile contains a pointer to the spinlock it is associated
with. Prepare support of differing spinlock_t and rspinlock_t types by
adding a type indicator of the pointer. Use the highest bit of the
block_cnt member for this indicator in order to not grow the struct
while hurting only th
Add rspin_is_locked() and rspin_barrier() in order to prepare differing
spinlock_t and rspinlock_t types.
Signed-off-by: Juergen Gross
---
V2:
- partially carved out from V1 patch, partially new
---
xen/arch/x86/mm/p2m-pod.c | 2 +-
xen/common/domain.c | 2 +-
xen/common/page_all
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