On 19.10.2023 02:07, Stefano Stabellini wrote:
> On Tue, 17 Oct 2023, Jan Beulich wrote:
>>> Jan, for this specific patch, I don't think we have the scan including
>>> Intel vmx files yet. Nicola please correct me if I am wrong. So Nicola
>>> wouldn't be able to easily expand this patch to also cov
On 19.10.2023 00:43, Stefano Stabellini wrote:
> On Mon, 16 Oct 2023, Jan Beulich wrote:
>> On 03.10.2023 17:24, Federico Serafini wrote:
>>> --- a/xen/arch/x86/mm.c
>>> +++ b/xen/arch/x86/mm.c
>>> @@ -5901,17 +5901,17 @@ int destroy_xen_mappings(unsigned long s, unsigned
>>> long e)
>>> * a pro
On 19.10.2023 02:44, Stefano Stabellini wrote:
> On Wed, 18 Oct 2023, Jan Beulich wrote:
>> On 18.10.2023 02:48, Stefano Stabellini wrote:
>>> On Mon, 16 Oct 2023, Jan Beulich wrote:
On 29.09.2023 00:24, Stefano Stabellini wrote:
> If it is not a MISRA requirement, then I think we should g
Hi Jan,
> On Oct 19, 2023, at 14:35, Jan Beulich wrote:
>
>> Also, should we consider it for xen 4.18? (I notice there is no for-4.18
>> tag).
>
> Of course we should, as it's a regression. I probably should have added
> the tag, despite my dislike for such. Intention was imo nevertheless
> cl
On 18.10.2023 23:31, Stefano Stabellini wrote:
> On Wed, 17 Oct 2023, Jan Beulich wrote:
>>
>> On 14.10.2023 01:06, Stefano Stabellini wrote:
>>> From: George Dunlap
>>>
>>> Commit fc2b57c9a ("xenstored: send an evtchn notification on
>>> introduce_domain") introduced the sending of an event chann
On 18.10.2023 18:12, Roger Pau Monné wrote:
> On Wed, Oct 18, 2023 at 05:11:58PM +0200, Jan Beulich wrote:
>> On 17.10.2023 10:29, Roger Pau Monne wrote:
>>> The mapping of memory regions below the 1MB mark was all done by the PVH
>>> dom0
>>> builder code, causing the region to be avoided by the
On 18.10.2023 20:00, Julien Grall wrote:
> On 18/10/2023 15:58, Jan Beulich wrote:
>> From: Manuel Bouyer
>>
>> The use of rcu_lock_domain_by_id() right in switch_serial_input() makes
>> assumptions about domain IDs which don't hold when in shim mode: The
>> sole (initial) domain there has a non-z
Signed-off-by: Henry Wang
---
CHANGELOG.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 165c5caf9b..47e98f036f 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -33,6 +33,7 @@ The format is based on [Keep a
Changelog](https://keepachangelog.com/en/1.0.0/)
Signed-off-by: Henry Wang
---
CHANGELOG.md | 8
1 file changed, 8 insertions(+)
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 3c83878c9b..48aff24f3a 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -4,6 +4,14 @@ Notable changes to Xen will be documented in this file.
The format is ba
Hi all,
This series should be the final CHANGELOG changes for 4.18.
The first patch is mentioning the MISRA-C improvement during the
4.18 dev cycle, so should be committed before we branch.
The second patch sets the release date and tag of 4.18 release and
should be included in both the staging
Signed-off-by: Henry Wang
---
CHANGELOG.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 47e98f036f..3c83878c9b 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -4,7 +4,7 @@ Notable changes to Xen will be documented in this file.
The forma
On Wed, 18 Oct 2023, Simone Ballarin wrote:
> Rule 13.1: Initializer lists shall not contain persistent side effects
>
> This patch moves expressions with side-effects outside the initializer lists.
>
> No functional changes.
>
> Signed-off-by: Simone Ballarin
> ---
> xen/common/sched/core.c
flight 183416 linux-linus real [real]
flight 183422 linux-linus real-retest [real]
http://logs.test-lab.xenproject.org/osstest/logs/183416/
http://logs.test-lab.xenproject.org/osstest/logs/183422/
Failures :-/ but no regressions.
Tests which are failing intermittently (not blocking):
test-armhf-
On Wed, 18 Oct 2023, Simone Ballarin wrote:
> Add const and pure attributes to address reports
> of MISRA C:2012 Rule 13.1: Initializer lists shall
> not contain persistent side effects
>
> Add pure attribute to function pdx_to_pfn.
> Add const attribute to functions generated by TYPE_SAFE.
>
> T
On Wed, 18 Oct 2023, Julien Grall wrote:
> Hi,
>
> On 18/10/2023 15:18, Simone Ballarin wrote:
> > Rule 13.1: Initializer lists shall not contain persistent side effects
> >
> > This patch moves expressions with side-effects into new variables before
> > the initializer lists.
>
> Looking at the
On Wed, 18 Oct 2023, Simone Ballarin wrote:
> Deviate violations of MISRA C:2012 Rule 13.1 caused by
> functions vcpu_runnable and __bad_atomic_size. These functions
> contain side-effects such as debugging logs, assertions and
> failures that cannot cause unexpected behaviors.
>
> Add "noeffect"
On Thu, 19 Oct 2023, andrew.coop...@citrix.com wrote:
> On 18/10/2023 2:42 pm, Nicola Vetrini wrote:
> > diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
> > index ee7aed0609d2..1b00e4e3e9b7 100644
> > --- a/docs/misra/deviations.rst
> > +++ b/docs/misra/deviations.rst
> > @@ -199
On Wed, 18 Oct 2023, Jan Beulich wrote:
> On 18.10.2023 02:48, Stefano Stabellini wrote:
> > On Mon, 16 Oct 2023, Jan Beulich wrote:
> >> On 29.09.2023 00:24, Stefano Stabellini wrote:
> >>> If it is not a MISRA requirement, then I think we should go for the path
> >>> of least resistance and try t
On Wed, 18 Oct 2023, Federico Serafini wrote:
> Add missing parameter names and remove inconsistencies between GICv3
> and GICv2. No functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Stefano Stabellini
Hi,
> On Oct 19, 2023, at 06:32, Stefano Stabellini wrote:
>
> On Wed, 18 Oct 2023, Andrew Cooper wrote:
>> On 06/10/2023 3:05 am, Marek Marczykowski-Górecki wrote:
>>> While working on tests for MSI-X, I did few cleanups of hw-based gitlab
>>> tests,
>>> greatly reducing false positive message
Hi,
> On Oct 19, 2023, at 02:00, Julien Grall wrote:
>
> Hi Jan,
>
> On 18/10/2023 15:58, Jan Beulich wrote:
>> From: Manuel Bouyer
>> The use of rcu_lock_domain_by_id() right in switch_serial_input() makes
>> assumptions about domain IDs which don't hold when in shim mode: The
>> sole (initia
On Wed, 18 Oct 2023, Julien Grall wrote:
> Hi Stefano,
>
> On 18/10/2023 01:55, Stefano Stabellini wrote:
> > On Tue, 17 Oct 2023, Julien Grall wrote:
> > > Hi Stefano,
> > >
> > > On 16/10/2023 21:47, Stefano Stabellini wrote:
> > > > On Mon, 16 Oct 2023, Bertrand Marquis wrote:
> > > > > > On 1
On Thu, Oct 19, 2023 at 12:30:22AM +0100, Andrew Cooper wrote:
> On 06/10/2023 3:05 am, Marek Marczykowski-Górecki wrote:
> > diff --git a/automation/scripts/qubes-x86-64.sh
> > b/automation/scripts/qubes-x86-64.sh
> > index 5464d10fc343..842e6fae7204 100755
> > --- a/automation/scripts/qubes-x86-
On Tue, 17 Oct 2023, Jan Beulich wrote:
> > Jan, for this specific patch, I don't think we have the scan including
> > Intel vmx files yet. Nicola please correct me if I am wrong. So Nicola
> > wouldn't be able to easily expand this patch to also cover Intel vmx
> > violations of this rule because
On Mon, 16 Oct 2023, Stefano Stabellini wrote:
> Please everyone fill in your preference here in advance of tomorrow's
> MISRA C meeting so we can discuss the results live:
> https://cryptpad.fr/form/#/2/form/view/kwflzAkvxhxF5U5Kv9O6QiQ5LEuCmHZlJhnNda7jk2g/
The results are ready. The following pe
On 06/10/2023 3:05 am, Marek Marczykowski-Górecki wrote:
> diff --git a/automation/scripts/qubes-x86-64.sh
> b/automation/scripts/qubes-x86-64.sh
> index 5464d10fc343..842e6fae7204 100755
> --- a/automation/scripts/qubes-x86-64.sh
> +++ b/automation/scripts/qubes-x86-64.sh
> @@ -90,23 +90,18 @@ on
On Wed, 2023-10-18 at 10:52 +0200, Kevin Wolf wrote:
> Am 16.10.2023 um 17:19 hat David Woodhouse geschrieben:
> > From: David Woodhouse
> >
> > There's no need to force the user to assign a vdev. We can automatically
> > assign one, starting at xvda and searching until we find the first disk
> >
On 18/10/2023 2:42 pm, Nicola Vetrini wrote:
> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
> index ee7aed0609d2..1b00e4e3e9b7 100644
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -199,6 +199,11 @@ Deviations related to MISRA C:2012 Rules:
>
On Mon, 16 Oct 2023, Jan Beulich wrote:
> On 03.10.2023 17:24, Federico Serafini wrote:
> > --- a/xen/arch/x86/mm.c
> > +++ b/xen/arch/x86/mm.c
> > @@ -5901,17 +5901,17 @@ int destroy_xen_mappings(unsigned long s, unsigned
> > long e)
> > * a problem.
> > */
> > void init_or_livepatch modify_
On Wed, 18 Oct 2023, Nicola Vetrini wrote:
> The constant 0 is used instead of NULL in '__ACCESS_ONCE' as a
> compile-time check to detect non-scalar types; its usage for this
> purpose is deviated.
>
> Furthermore, the 'typeof_field' macro is introduced as a general way
> to access the type of a
On Wed, 18 Oct 2023, Andrew Cooper wrote:
> On 06/10/2023 3:05 am, Marek Marczykowski-Górecki wrote:
> > While working on tests for MSI-X, I did few cleanups of hw-based gitlab
> > tests,
> > greatly reducing false positive messages in the test output.
> >
> > After applying this series, the tests
flight 183420 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183420/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf b75d9f556d6f290a4037064a2b934f5a3396328c
baseline version:
ovmf 7fe49887c4d227e585d5a
As mentioned in the linux kernel development document, "sched_clock() is
used for scheduling and timestamping". While there is a default native
implementation, many paravirtualizations have their own implementations.
About KVM, it uses kvm_sched_clock_read() and there is no way to only
disable KVM
On Wed, Oct 18, 2023 at 06:45:03PM +0100, Andrew Cooper wrote:
> On 06/10/2023 3:05 am, Marek Marczykowski-Górecki wrote:
> > grep+sleep message every 1s makes job log unnecessary hard to read.
> >
> > Signed-off-by: Marek Marczykowski-Górecki
> > ---
> > I know I can download serial log file, but
flight 183419 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183419/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-libvirt 15 migrate-support-checkfail never pass
test-arm64-arm64-xl-xsm 1
On Wed, 18 Oct 2023, Julien Grall wrote:
> On 18/10/2023 13:52, Nicola Vetrini wrote:
> > On 18/10/2023 14:38, Julien Grall wrote:
> > > Hi Nicola,
> > >
> > > On 18/10/2023 13:30, Nicola Vetrini wrote:
> > > > On 17/10/2023 15:28, Julien Grall wrote:
> > > > I tested this, and the report is preve
On Wed, 17 Oct 2023, Jan Beulich wrote:
>
> On 14.10.2023 01:06, Stefano Stabellini wrote:
> > From: George Dunlap
> >
> > Commit fc2b57c9a ("xenstored: send an evtchn notification on
> > introduce_domain") introduced the sending of an event channel to the
> > guest when first introduced, so tha
flight 183417 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183417/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 7fe49887c4d227e585d5aa5530ee8a8d79d5fa1e
baseline version:
ovmf 747a08eae26bda91c53d2
On 16/10/2023 19:45, Julien Grall wrote:
Hi,
Hi Julien,
On 11/09/2023 14:59, Ayan Kumar Halder wrote:
This is based on
"[PATCH v6 03/13] xen/arm64: Split and move MMU-specific head.S to
mmu/head.S"
https://www.mail-archive.com/xen-devel@lists.xenproject.org/msg151920.html
Same remark
Hi,
On 18/10/2023 11:59, Julien Grall wrote:
On 17/10/2023 20:58, Stefano Stabellini wrote:
And therefore a Fixes tag is sensible. This doesn't mean I would want to
backport it right now (note that only 4.18 is affected). But this
could change
in the future if we get another report (post-4.18)
Hi Jan,
On 18/10/2023 15:58, Jan Beulich wrote:
From: Manuel Bouyer
The use of rcu_lock_domain_by_id() right in switch_serial_input() makes
assumptions about domain IDs which don't hold when in shim mode: The
sole (initial) domain there has a non-zero ID. Obtain the real domain ID
in that case
On 06/10/2023 3:05 am, Marek Marczykowski-Górecki wrote:
> While working on tests for MSI-X, I did few cleanups of hw-based gitlab tests,
> greatly reducing false positive messages in the test output.
>
> After applying this series, the tests-artifacts/alpine/3.18 container needs to
> be rebuilt.
>
On 06/10/2023 3:05 am, Marek Marczykowski-Górecki wrote:
> grep+sleep message every 1s makes job log unnecessary hard to read.
>
> Signed-off-by: Marek Marczykowski-Górecki
> ---
> I know I can download serial log file, but that's 3 more clicks...
> ---
> automation/scripts/qubes-x86-64.sh | 2 ++
Hi Stefano,
On 18/10/2023 01:55, Stefano Stabellini wrote:
On Tue, 17 Oct 2023, Julien Grall wrote:
Hi Stefano,
On 16/10/2023 21:47, Stefano Stabellini wrote:
On Mon, 16 Oct 2023, Bertrand Marquis wrote:
On 16 Oct 2023, at 15:38, Julien Grall wrote:
On 16/10/2023 14:31, Bertrand Marquis
flight 183414 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183414/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 747a08eae26bda91c53d232d3bd65946183693d0
baseline version:
ovmf 01e1bc28943a6bd66830e
On 18/10/2023 5:07 pm, Roger Pau Monne wrote:
> Enabling 5 level paging support (AGAW 3) at this point in the release is too
> risky,
This comment will go stale extremely quickly.
"It is too late in the Xen 4.18 release to enable support for 5 level
paging, ..."
~Andrew
> so instead put a bodg
Hi Frederico,
> On 18 Oct 2023, at 14:50, Federico Serafini
> wrote:
>
> Add missing parameter names. No functional change.
>
> Signed-off-by: Federico Serafini
Reviewed-by: Bertrand Marquis
Cheers
Bertrand
> ---
> Changes in v2:
> - fixed names.
> ---
> xen/arch/arm/include/asm/cpufeatur
On Wed, Oct 18, 2023 at 05:11:58PM +0200, Jan Beulich wrote:
> On 17.10.2023 10:29, Roger Pau Monne wrote:
> > The mapping of memory regions below the 1MB mark was all done by the PVH
> > dom0
> > builder code, causing the region to be avoided by the arch specific IOMMU
> > hardware domain initial
SAGAW is a bitmap field, with bits 1, 2 and 3 signaling support for 3, 4 and 5
level page tables respectively. According to the Intel VT-d specification, an
IOMMU can report multiple SAGAW bits being set.
Commit 859d11b27912 claims to replace the open-coded find_first_set_bit(), but
it's actually
flight 183408 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183408/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt 16 saverestore-support-checkfail like 183403
test-amd64-amd64-xl-qemut-win7-amd64
On 13.10.2023 11:42, Juergen Gross wrote:
> Use named member initializers instead of positional ones for the macros
> used to initialize structures.
>
> Signed-off-by: Juergen Gross
Acked-by: Jan Beulich
On 13.10.2023 11:42, Juergen Gross wrote:
> With some small adjustments to the LOCK_PROFILE_* macros some #ifdefs
> can be dropped from spinlock.c.
>
> Signed-off-by: Juergen Gross
> ---
> V2:
> - new patch
> ---
> xen/common/spinlock.c | 45 ++-
> 1 file
On 18/10/23 02:55, Stefano Stabellini wrote:
On Tue, 17 Oct 2023, Julien Grall wrote:
Hi Stefano,
On 16/10/2023 21:47, Stefano Stabellini wrote:
On Mon, 16 Oct 2023, Bertrand Marquis wrote:
On 16 Oct 2023, at 15:38, Julien Grall wrote:
On 16/10/2023 14:31, Bertrand Marquis wrote:
Hi Juli
On 18.10.23 17:47, Jan Beulich wrote:
On 13.10.2023 11:42, Juergen Gross wrote:
Fix some coding style issues in spinlock coding:
- Instead of u64 etc. use the preferred uint64_t etc. types
- Remove some trailing spaces
- Add missing spaces in "if" statements
- Add some missing blank lines
Sign
On 13.10.2023 11:42, Juergen Gross wrote:
> Fix some coding style issues in spinlock coding:
>
> - Instead of u64 etc. use the preferred uint64_t etc. types
> - Remove some trailing spaces
> - Add missing spaces in "if" statements
> - Add some missing blank lines
>
> Signed-off-by: Juergen Gross
On 13.10.2023 20:13, Shawn Anastasio wrote:
> --- /dev/null
> +++ b/xen/arch/ppc/ppc64/exceptions-asm.S
> @@ -0,0 +1,129 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +
> +#include
> +#include
> +
> +.section .text.exceptions, "ax", %progbits
> +
> +/* Helper to dump CPU state t
On 18/10/2023 16:56, Jan Beulich wrote:
On 18.10.2023 16:28, Nicola Vetrini wrote:
On 16/10/2023 16:58, Jan Beulich wrote:
On 09.10.2023 08:54, Nicola Vetrini wrote:
These variables are only used by asm code, and therefore
the lack of a declaration is justified by the corresponding
deviation c
On 13.10.2023 20:13, Shawn Anastasio wrote:
> On Power, the exception vectors must lie at a fixed address, depending
> on the state of the Alternate Interrupt Location (AIL) field of the
> Logical Partition Control Register (LPCR). Create a .text.exceptions
> section in the linker script at an addr
On 18.10.2023 15:42, Nicola Vetrini wrote:
> The constant 0 is used instead of NULL in '__ACCESS_ONCE' as a
> compile-time check to detect non-scalar types; its usage for this
> purpose is deviated.
>
> Furthermore, the 'typeof_field' macro is introduced as a general way
> to access the type of a
On 17.10.2023 10:29, Roger Pau Monne wrote:
> The mapping of memory regions below the 1MB mark was all done by the PVH dom0
> builder code, causing the region to be avoided by the arch specific IOMMU
> hardware domain initialization code. That lead to the IOMMU being enabled
> without reserved reg
Hi,
On 18/10/2023 15:18, Simone Ballarin wrote:
Rule 13.1: Initializer lists shall not contain persistent side effects
This patch moves expressions with side-effects into new variables before
the initializer lists.
Looking at the code, I feel the commit message should be a bit more
verbose b
From: Manuel Bouyer
The use of rcu_lock_domain_by_id() right in switch_serial_input() makes
assumptions about domain IDs which don't hold when in shim mode: The
sole (initial) domain there has a non-zero ID. Obtain the real domain ID
in that case (generalized as get_initial_domain_id() returns ze
On 18.10.2023 16:28, Nicola Vetrini wrote:
> On 16/10/2023 16:58, Jan Beulich wrote:
>> On 09.10.2023 08:54, Nicola Vetrini wrote:
>>> These variables are only used by asm code, and therefore
>>> the lack of a declaration is justified by the corresponding
>>> deviation comment.
>>
>> Hmm, you say "
On 18.10.2023 16:18, Michal Orzel wrote:
> On 18/10/2023 15:29, Jan Beulich wrote:
>> On 18.10.2023 12:38, Manuel Bouyer wrote:
>>> Hello,
>>> With Xen 4.18, a PV domain running under pvshim doesn't get console input.
>>> This is because the domain id in pvshim isn't 0 (and on x86 max_init_domid
>
On Wed, Oct 18, 2023 at 04:18:26PM +0200, Michal Orzel wrote:
> Hi,
>
> On 18/10/2023 15:29, Jan Beulich wrote:
> >
> >
> > On 18.10.2023 12:38, Manuel Bouyer wrote:
> >> Hello,
> >> With Xen 4.18, a PV domain running under pvshim doesn't get console input.
> >> This is because the domain id in
On 16/10/2023 16:58, Jan Beulich wrote:
On 09.10.2023 08:54, Nicola Vetrini wrote:
These variables are only used by asm code, and therefore
the lack of a declaration is justified by the corresponding
deviation comment.
Hmm, you say "declaration" here, but according to my understanding ...
--
Add missing parameter names. No functional change.
Signed-off-by: Federico Serafini
---
xen/arch/x86/include/asm/mtrr.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/xen/arch/x86/include/asm/mtrr.h b/xen/arch/x86/include/asm/mtrr.h
index 14246e3387..1d2744eceb 10
Add missing parameter names. No functional change.
Signed-off-by: Federico Serafini
---
xen/arch/x86/include/asm/cpuidle.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/xen/arch/x86/include/asm/cpuidle.h
b/xen/arch/x86/include/asm/cpuidle.h
index 3edd7a75d2..70
This patch series addresses some of the violations of Rule 8.2 adding the
missing parameter names.
Federico Serafini (7):
x86/mctelem: address violations of MISRA C:2012 Rule 8.2
x86/mtrr: address violation of MISRA C:2012 Rule 8.2
x86/domain: address violations of MISRA C:2012 Rule 8.2
x8
Add missing parameter names. No functional change.
Signed-off-by: Federico Serafini
---
xen/arch/x86/cpu/mcheck/vmce.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/cpu/mcheck/vmce.h b/xen/arch/x86/cpu/mcheck/vmce.h
index 2e9b32a9bd..a9a325f776 100644
-
Add missing parameter name. No functional change.
Signed-off-by: Federico Serafini
---
xen/arch/x86/cpu/mcheck/mcaction.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/x86/cpu/mcheck/mcaction.h
b/xen/arch/x86/cpu/mcheck/mcaction.h
index 5cbe558fb0..9cb2ad6c9f 1006
Add missing parameter names. No functional change.
Signed-off-by: Federico Serafini
---
xen/arch/x86/hpet.c | 2 +-
xen/arch/x86/include/asm/hpet.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/hpet.c b/xen/arch/x86/hpet.c
index 79c07f6a9e..63d41
Add missing parameter names. No functional change.
Signed-off-by: Federico Serafini
---
xen/arch/x86/include/asm/domain.h | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/xen/arch/x86/include/asm/domain.h
b/xen/arch/x86/include/asm/domain.h
index
Add missing parameter names. No functional change.
Signed-off-by: Federico Serafini
---
xen/arch/x86/cpu/mcheck/mctelem.c | 2 +-
xen/arch/x86/cpu/mcheck/mctelem.h | 25 +
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/xen/arch/x86/cpu/mcheck/mctelem.c
Add const and pure attributes to address reports
of MISRA C:2012 Rule 13.1: Initializer lists shall
not contain persistent side effects
Add pure attribute to function pdx_to_pfn.
Add const attribute to functions generated by TYPE_SAFE.
These functions are used in initializer lists: adding
the att
Rule 13.1: Initializer lists shall not contain persistent side effects
This patch moves expressions with side-effects outside the initializer lists.
No functional changes.
Signed-off-by: Simone Ballarin
---
xen/common/sched/core.c| 16
xen/drivers/char/ns16550.c | 4 +++-
This series contains some changes and deviation to address
reports of MISRA C:2012 Rule 13.1:
Initializer lists shall not contain persistent side effects
Some expressions with side-effects have been moved outside the
initializer lists, others have been deviated.
Function calls do not necessarily
Deviate violations of MISRA C:2012 Rule 13.1 caused by
functions vcpu_runnable and __bad_atomic_size. These functions
contain side-effects such as debugging logs, assertions and
failures that cannot cause unexpected behaviors.
Add "noeffect" call property to functions read_u.*_atomic and
get_cycle
Rule 13.1: Initializer lists shall not contain persistent side effects
This patch moves expressions with side-effects into new variables before
the initializer lists.
Function calls do not necessarily have side-effects, in these cases the
GCC pure or const attributes are added when possible.
No
Hi,
On 18/10/2023 15:29, Jan Beulich wrote:
>
>
> On 18.10.2023 12:38, Manuel Bouyer wrote:
>> Hello,
>> With Xen 4.18, a PV domain running under pvshim doesn't get console input.
>> This is because the domain id in pvshim isn't 0 (and on x86 max_init_domid is
>> hardwired to 0), so console_inpu
On Wed, Oct 18, 2023 at 03:51:54PM +0200, Jan Beulich wrote:
> On 18.10.2023 15:36, Manuel Bouyer wrote:
> > On Wed, Oct 18, 2023 at 03:24:22PM +0200, Jan Beulich wrote:
> >> On 18.10.2023 13:20, Manuel Bouyer wrote:
> >>> On Wed, Oct 18, 2023 at 11:44:22AM +0100, Andrew Cooper wrote:
> On 18/
On 18.10.2023 15:36, Manuel Bouyer wrote:
> On Wed, Oct 18, 2023 at 03:24:22PM +0200, Jan Beulich wrote:
>> On 18.10.2023 13:20, Manuel Bouyer wrote:
>>> On Wed, Oct 18, 2023 at 11:44:22AM +0100, Andrew Cooper wrote:
On 18/10/2023 11:38 am, Manuel Bouyer wrote:
> Hello,
> With Xen 4.18
The constant 0 is used instead of NULL in '__ACCESS_ONCE' as a
compile-time check to detect non-scalar types; its usage for this
purpose is deviated.
Furthermore, the 'typeof_field' macro is introduced as a general way
to access the type of a struct member without declaring a variable
of struct ty
On Wed, Oct 18, 2023 at 03:29:08PM +0200, Jan Beulich wrote:
> On 18.10.2023 12:38, Manuel Bouyer wrote:
> > Hello,
> > With Xen 4.18, a PV domain running under pvshim doesn't get console input.
> > This is because the domain id in pvshim isn't 0 (and on x86 max_init_domid
> > is
> > hardwired to
On Wed, Oct 18, 2023 at 03:24:22PM +0200, Jan Beulich wrote:
> On 18.10.2023 13:20, Manuel Bouyer wrote:
> > On Wed, Oct 18, 2023 at 11:44:22AM +0100, Andrew Cooper wrote:
> >> On 18/10/2023 11:38 am, Manuel Bouyer wrote:
> >>> Hello,
> >>> With Xen 4.18, a PV domain running under pvshim doesn't ge
On 18.10.2023 12:38, Manuel Bouyer wrote:
> Hello,
> With Xen 4.18, a PV domain running under pvshim doesn't get console input.
> This is because the domain id in pvshim isn't 0 (and on x86 max_init_domid is
> hardwired to 0), so console_input_domain() will never select that domain
> as input.
>
>
On 18.10.2023 13:20, Manuel Bouyer wrote:
> On Wed, Oct 18, 2023 at 11:44:22AM +0100, Andrew Cooper wrote:
>> On 18/10/2023 11:38 am, Manuel Bouyer wrote:
>>> Hello,
>>> With Xen 4.18, a PV domain running under pvshim doesn't get console input.
>>> This is because the domain id in pvshim isn't 0 (a
Add missing parameter names and remove inconsistencies between GICv3
and GICv2. No functional change.
Signed-off-by: Federico Serafini
---
Changes in v2:
- switched parameter names of gicv3_write_lr().
---
xen/arch/arm/gic-v3.c | 22 +++---
xen/arch/arm/include/asm/gic.h
Hi,
On 18/10/2023 13:52, Nicola Vetrini wrote:
On 18/10/2023 14:38, Julien Grall wrote:
Hi Nicola,
On 18/10/2023 13:30, Nicola Vetrini wrote:
On 17/10/2023 15:28, Julien Grall wrote:
I tested this, and the report is prevented by the ASSERT. It's up to
the maintainers to
decide how do you wa
On 18/10/2023 14:38, Julien Grall wrote:
Hi Nicola,
On 18/10/2023 13:30, Nicola Vetrini wrote:
On 17/10/2023 15:28, Julien Grall wrote:
I tested this, and the report is prevented by the ASSERT. It's up to
the maintainers to
decide how do you want to proceed: my suggestion is deviating it,
I
Add missing parameter names. No functional change.
Signed-off-by: Federico Serafini
---
Changes in v2:
- fixed names.
---
xen/arch/arm/include/asm/cpufeature.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/include/asm/cpufeature.h
b/xen/arch/arm/includ
Hi Nicola,
On 18/10/2023 13:30, Nicola Vetrini wrote:
On 17/10/2023 15:28, Julien Grall wrote:
I tested this, and the report is prevented by the ASSERT. It's up to the
maintainers to
decide how do you want to proceed: my suggestion is deviating it,
It is not clear to me what would you deviat
On 17/10/2023 15:28, Julien Grall wrote:
Hi Jan,
On 17/10/2023 07:11, Jan Beulich wrote:
On 16.10.2023 20:06, Julien Grall wrote:
Instead, it would be best to find a way to help Eclair to detect this
is
not an issue and also improve readability. Would the following help
Eclair?
diff --git a
On 18.10.2023 12:59, Andrew Cooper wrote:
> On 17/08/2023 7:22 am, Jan Beulich wrote:
>> --- a/xen/lib/x86/cpuid.c
>> +++ b/xen/lib/x86/cpuid.c
>> @@ -104,6 +104,22 @@ void x86_cpu_featureset_to_policy(
>> p->feat._7d1 = fs[FEATURESET_7d1];
>> p->arch_caps.lo = fs[FEA
flight 183407 libvirt real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183407/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt-qcow2 15 saverestore-support-check fail like 183395
test-armhf-armhf-libvirt-raw 15 saveresto
On 17/10/2023 4:09 pm, Alejandro Vallejo wrote:
> The page is pretty nice overall and I quite liked it. Just a few extra
> questions below, as I'm not familiar with this side of things,
>
> On Mon, Oct 16, 2023 at 05:24:50PM +0100, Andrew Cooper wrote:
>> Signed-off-by: Andrew Cooper
>> ---
>> CC:
Hi Andrew,
> On Oct 18, 2023, at 19:23, Andrew Cooper wrote:
>
> On 18/10/2023 12:20 pm, Manuel Bouyer wrote:
>> On Wed, Oct 18, 2023 at 11:44:22AM +0100, Andrew Cooper wrote:
>>> On 18/10/2023 11:38 am, Manuel Bouyer wrote:
Hello,
With Xen 4.18, a PV domain running under pvshim doesn'
On 18/10/2023 12:20 pm, Manuel Bouyer wrote:
> On Wed, Oct 18, 2023 at 11:44:22AM +0100, Andrew Cooper wrote:
>> On 18/10/2023 11:38 am, Manuel Bouyer wrote:
>>> Hello,
>>> With Xen 4.18, a PV domain running under pvshim doesn't get console input.
>>> This is because the domain id in pvshim isn't 0
On Wed, Oct 18, 2023 at 11:44:22AM +0100, Andrew Cooper wrote:
> On 18/10/2023 11:38 am, Manuel Bouyer wrote:
> > Hello,
> > With Xen 4.18, a PV domain running under pvshim doesn't get console input.
> > This is because the domain id in pvshim isn't 0 (and on x86 max_init_domid
> > is
> > hardwire
flight 183410 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/183410/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 01e1bc28943a6bd66830e8af56665dc9e4647a08
baseline version:
ovmf 772ec92577a8c786b6c9f
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