On 07.08.2025 18:59, Milan Djokic wrote:
> --- a/xen/include/xen/iommu.h
> +++ b/xen/include/xen/iommu.h
> @@ -311,6 +311,15 @@ static inline int iommu_add_dt_pci_sideband_ids(struct
> pci_dev *pdev)
>
> #endif /* HAS_DEVICE_TREE_DISCOVERY */
>
> +#ifdef CONFIG_ARM
> +struct iommu_guest_confi
On 07.08.2025 18:59, Milan Djokic wrote:
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -2058,6 +2058,13 @@ This option can be specified more than once (up to 8
> times at present).
>
> Flag to enable or disable support for PCI passthrough
>
> +### vi
On 07.08.2025 18:59, Milan Djokic wrote:
> --- a/xen/drivers/passthrough/Kconfig
> +++ b/xen/drivers/passthrough/Kconfig
> @@ -35,6 +35,12 @@ config IPMMU_VMSA
> (H3 ES3.0, M3-W+, etc) or Gen4 SoCs which IPMMU hardware supports
> stage 2
> translation table format and is able to us
On 07.08.2025 18:20, Oleksii Kurochko wrote:
>
> On 8/6/25 10:12 AM, Jan Beulich wrote:
>> On 06.08.2025 09:45, Oleksii Kurochko wrote:
>>> On 8/6/25 8:05 AM, Jan Beulich wrote:
Overall: There are very many items on this list, and it seems entirely
clear to
me that not all of them
On Mon, 4 Aug 2025 23:50:09 -0500
Aaron Rainbolt wrote:
> Xen traditionally allows customizing guest behavior by passing
> arguments to the VM kernel via the kernel command line. This is no
> longer possible when using GRUB with Xen, as the kernel command line
> is decided by the GRUB configurati
From: Denis Mukhin
Introduce some basic infrastructure for doing domain ID allocation unit tests,
and add a few tests that ensure correctness of the domain ID allocator.
Use and xen/lib/find-next-bit.c in test hardness code.
Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.
Signed-of
From: Denis Mukhin
Use %pd for domain identification in error/panic messages in create_dom0().
No functional change.
Signed-off-by: Denis Mukhin
Reviewed-by: Alejandro Vallejo
Acked-by: Jan Beulich
---
Changes since v13:
- n/a
---
xen/arch/arm/domain_build.c | 6 +++---
xen/arch/x86/setup.
Patch 1 introduces new domid_{alloc,free} calls.
Patch 2 is a prep change for domain ID allocator test.
Patch 3 introduces some basic testing for domain ID allocator.
Patch 4 adjusts create_dom0() messages (use %pd).
Link to v13:
https://lore.kernel.org/xen-devel/20250730174042.1632011-1-dmuk...@
From: Denis Mukhin
Move xc_bitops.h to common tools location to be shared between
the toolstack and unit test code.
Adjust the guard in xen-tools/bitops.h
Correct the #include directives and comments referring to the old
xc_bitops.h in the toolstack code.
Signed-off-by: Denis Mukhin
---
Chan
From: Denis Mukhin
Currently, there are two different domain ID allocation implementations:
1) Sequential IDs allocation in dom0less Arm code based on max_init_domid;
2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
max_init_domid (both Arm and x86).
The domain I
On Thu, Aug 07, 2025 at 11:53:56PM +0200, Nicola Vetrini wrote:
> The clean target also clears files outside the xen directory,
> which is not needed for the purposes of running an analysis.
>
> No functional change.
>
> Reported-by: Andrew Cooper
> Signed-off-by: Nicola Vetrini
Reviewed-by: D
On 2025-08-07 05:19, Jan Beulich wrote:
On 07.08.2025 03:56, Jason Andryuk wrote:
--- a/xen/include/public/io/console.h
+++ b/xen/include/public/io/console.h
@@ -19,6 +19,19 @@ struct xencons_interface {
char out[2048];
XENCONS_RING_IDX in_cons, in_prod;
XENCONS_RING_IDX out_co
On 2025-08-07 03:00, Jürgen Groß wrote:
On 07.08.25 03:56, Jason Andryuk wrote:
With hyperlaunch, a domU can start before its console ring is connected
by xenconsoled. With nothing emptying the ring, it can quickly fill
during boot. In domU_write_console(), __write_console() returns 0 when
the
The clean target also clears files outside the xen directory,
which is not needed for the purposes of running an analysis.
No functional change.
Reported-by: Andrew Cooper
Signed-off-by: Nicola Vetrini
---
automation/eclair_analysis/prepare.sh | 4 ++--
1 file changed, 2 insertions(+), 2 delet
From: Mykola Kvach
The "xl resume" command was previously excluded from Arm builds because
system suspend/resume (e.g., SYSTEM_SUSPEND via vPSCI) was not
implemented. On x86, this command is used for resume.
This change enables compilation of `xl resume` on Arm regardless of the
underlying imple
On Mon, Aug 04, 2025 at 12:23:34PM +0200, Jan Beulich wrote:
> On 31.07.2025 21:22, dm...@proton.me wrote:
> > From: Denis Mukhin
> >
> > Added missing definitions needed for NS16550 UART emulator.
> >
> > Newly introduced MSR definitions re-used in the existing ns16550 driver.
> >
> > Also, corre
From: Mykola Kvach
Mention the newly added support for guest suspend and resume to/from
RAM via vPSCI on Arm platforms.
This support is limited to non-hardware domain guests.
Signed-off-by: Mykola Kvach
Acked-by: Oleksii Kurochko
---
Chnages in v6:
- removed reduntand explanation that thi sup
From: Mykola Kvach
This patch series introduces the initial support for guest suspend
and resume on ARM platforms using the PSCI SYSTEM_SUSPEND interface. The main
goal is to allow ARM guests to request suspension using PSCI and be resumed
by the control domain (e.g., via "xl resume").
### Backg
From: Mykola Kvach
Add a new entry under the "Virtual Hardware, QEMU" section documenting
support for the optional PSCI SYSTEM_SUSPEND function exposed to guests.
This function is available via the virtual PSCI (vPSCI) interface and
allows guest domains (domUs) to initiate system suspend operati
From: Mykola Kvach
This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPSCI
(virtual PSCI) interface, allowing guests to request suspend via the PSCI
v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).
The implementation:
- Adds SYSTEM_SUSPEND function IDs to PSCI defini
On Mon, Aug 04, 2025 at 01:06:32PM +0200, Jan Beulich wrote:
> On 31.07.2025 21:22, dm...@proton.me wrote:
> > From: Denis Mukhin
> >
> > Enable virtual NS16550 for PVH domains in xl.
> >
> > {map,unmap}_domain_emuirq_pirq() infrastructure is modified by adding new
> > type of interrupt resources
On Wed, Aug 06, 2025 at 04:24:52PM +0200, Roger Pau Monné wrote:
> On Thu, Jul 31, 2025 at 07:21:49PM +, dm...@proton.me wrote:
> > From: Denis Mukhin
> >
> > Introduce a driver framework to abstract UART emulators in the hypervisor.
> >
> > That allows for architecture-independent handling of
On 16/05/2025 9:31 am, Roger Pau Monne wrote:
> diff --git a/xen/arch/x86/pci.c b/xen/arch/x86/pci.c
> index 97b792e578f1..afaf9fe1c053 100644
> --- a/xen/arch/x86/pci.c
> +++ b/xen/arch/x86/pci.c
> @@ -98,3 +98,53 @@ int pci_conf_write_intercept(unsigned int seg, unsigned
> int bdf,
>
> re
On Mon, Aug 04, 2025 at 12:20:11PM +0200, Jan Beulich wrote:
> On 31.07.2025 21:21, dm...@proton.me wrote:
> > From: Denis Mukhin
> >
> > Move IRQ/IOMEM rangesets allocation before arch_domain_create().
> >
> > That guarantees that arch-specific code could access those rangesets to
> > register tr
On Wed, Aug 06, 2025 at 04:37:23PM +0200, Roger Pau Monné wrote:
> On Thu, Jul 31, 2025 at 07:21:54PM +, dm...@proton.me wrote:
> > From: Denis Mukhin
> >
> > Move IRQ/IOMEM rangesets allocation before arch_domain_create().
> >
> > That guarantees that arch-specific code could access those ran
On Wed, Aug 06, 2025 at 05:06:24PM +0200, Roger Pau Monné wrote:
[..]
> > @@ -0,0 +1,1009 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * NS16550-compatible UART Emulator.
> > + *
> > + * See:
> > + * - Serial and UART Tutorial:
> > + *
> > https://download.freebsd.org/doc/
From: Rahul Singh
Event queue is used to send the events to guest when there is an events/
faults. Add support for event queue to send events to guest.
Global error in SMMUv3 hw will be updated in smmu_gerror and
smmu_gerrorn register. Add support for global error registers to send
global error
From: Rahul Singh
Add new viommu_type field and field values XEN_DOMCTL_CONFIG_VIOMMU_NONE
XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3 in xen_arch_domainconfig to
enable/disable vIOMMU support for domains.
Also add viommu="N" parameter to xl domain configuration to enable the
vIOMMU for the domains. Current
From: Rahul Singh
Xen SMMUv3 driver only supports stage-2 translation. Add support for
Stage-1 translation that is required to support nested stage
translation.
In true nested mode, both s1_cfg and s2_cfg will coexist.
Let's remove the union. When nested stage translation is setup, both
s1_cfg a
From: Rahul Singh
XEN will create an Emulated SMMUv3 device tree node in the device tree
to enable the dom0less domains to discover the virtual SMMUv3 during
boot. Emulated SMMUv3 device tree node will only be created when cmdline
option vsmmuv3 is enabled.
Signed-off-by: Rahul Singh
Signed-off
From: Rahul Singh
CMD_CFGI_STE is used to invalidate/validate the STE. Emulated vSMMUv3
driver in XEN will read the STE from the guest memory space and capture
the Stage-1 configuration required to support nested translation.
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
xen/driv
From: Rahul Singh
Attach the Stage-1 configuration to device STE to support nested
translation for the guests.
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
xen/drivers/passthrough/arm/smmu-v3.c | 79 ++
xen/drivers/passthrough/arm/smmu-v3.h | 1 +
xen/
From: Rahul Singh
Add cmdline boot option "viommu = " to enable or disable the
virtual iommu support for guests on ARM.
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
docs/misc/xen-command-line.pandoc | 7 +++
xen/arch/arm/include/asm/viommu.h | 11 +++
xen/
From: Rahul Singh
This patch adds basic framework for vIOMMU.
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
xen/arch/arm/dom0less-build.c| 2 +
xen/arch/arm/domain.c| 25 ++
xen/arch/arm/domain_build.c | 2 +
xen/arch/arm/include/asm/vio
From: Rahul Singh
To configure IOMMU in guest for passthrough devices, user will need to
copy the unmodified "iommus" property from host device tree to partial
device tree. To enable the dom0 linux kernel to confiure the IOMMU
correctly replace the phandle in partial device tree with virtual
IOMM
From: Rahul Singh
Stage-1 translation is handled by guest, therefore stage-1 fault has to
be forwarded to guest.
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
xen/drivers/passthrough/arm/smmu-v3.c | 48 --
xen/drivers/passthrough/arm/vsmmu-v3.c | 45 +
From: Rahul Singh
To configure IOMMU in guest for passthrough devices, user will need to
copy the unmodified "iommus" property from host device tree to partial
device tree. To enable the dom0 linux kernel to confiure the IOMMU
correctly replace the phandle in partial device tree with virtual
IOMM
From: Rahul Singh
libxl will create an Emulated SMMUv3 device tree node in the device
tree to enable the guest OS to discover the virtual SMMUv3 during guest
boot.
Emulated SMMUv3 device tree node will only be created when
"viommu=smmuv3" is set in xl domain configuration.
Signed-off-by: Rahul
From: Rahul Singh
XEN will create an IOMMU device tree node in the device tree
to enable the dom0 to discover the virtual SMMUv3 during dom0 boot.
IOMMU device tree node will only be created when cmdline option viommu
is enabled.
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
xen/
From: Rahul Singh
domain_viommu_init() will be called during domain creation and will add
the dummy trap handler for virtual IOMMUs for guests.
A host IOMMU list will be created when host IOMMU devices are probed
and this list will be used to create the IOMMU device tree node for
dom0. For dom0,
This patch series represents a rebase of an older patch series implemented and
sumbitted by Rahul Singh as an RFC:
https://patchwork.kernel.org/project/xen-devel/cover/cover.1669888522.git.rahul.si...@arm.com/.
Original patch series content is aligned with the latest xen structure in terms
of com
From: Rahul Singh
Alloc and reserve virq for event queue and global error to send event to
guests. Also Modify the libxl to accomadate the new define virq.
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
tools/libs/light/libxl_arm.c | 28 --
xen/ar
From: Rahul Singh
Add initial support for various emulated registers for virtual SMMUv3
for guests and also add support for virtual cmdq and eventq.
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
xen/drivers/passthrough/arm/smmu-v3.h | 6 +
xen/drivers/passthrough/arm/vsmmu-v3.
From: Rahul Singh
"iommus" property will be added for dom0 devices to virtual
IOMMU node to enable the dom0 linux kernel to configure the IOMMU
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
xen/arch/arm/domain_build.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
From: Jean-Philippe Brucker
Backport Linux commit cdf315f907d4. This is the clean backport without
any changes.
When handling faults from the event or PRI queue, we need to find the
struct device associated with a SID. Add a rb_tree to keep track of
SIDs.
Acked-by: Jonathan Cameron
Reviewed-by
From: Rahul Singh
Add support for virtual cmdqueue handling for guests
Signed-off-by: Rahul Singh
Signed-off-by: Milan Djokic
---
xen/drivers/passthrough/arm/vsmmu-v3.c | 101 +
1 file changed, 101 insertions(+)
diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c
b/x
From: Rahul Singh
In current implementation io_domain is allocated once for each xen
domain as Stage2 translation is common for all devices in same xen
domain.
Nested stage supports S1 and S2 configuration at the same time. Stage1
translation will be different for each device as linux kernel wil
Hi Milan,
On Thu, 7 Aug 2025 at 17:55, Milan Djokic wrote:
> This patch series represents a rebase of an older patch series implemented
> and
> sumbitted by Rahul Singh as an RFC:
> https://patchwork.kernel.org/project/xen-devel/cover/cover.1669888522.git.rahul.si...@arm.com/
> .
> Original patc
In case of ARM_32, all of the RAM will be covered by a permanent contiguous
mapping (where VA == PA) and there will be a single heap. Thus, the memory
allocated from Xen heap uses PGC_xen_heap.
This is similar to the scenario described for
"CONFIG_SEPARATE_XENHEAP=n W/ DIRECT MAP OF ALL RAM" in com
On Wed, Aug 06, 2025 at 03:56:42PM +0200, Roger Pau Monné wrote:
> On Tue, Aug 05, 2025 at 12:54:31AM +, dm...@proton.me wrote:
> > + Cc: Oleskii
> >
> > On Mon, Aug 04, 2025 at 11:46:36AM +0200, Jan Beulich wrote:
> > > On 31.07.2025 21:21, dm...@proton.me wrote:
> > > > --- a/xen/include/xen/
There is no domheap for ARM_32. All of the RAM is mapped and VA == PA.
Signed-off-by: Ayan Kumar Halder
---
xen/arch/arm/Kconfig | 2 +-
xen/arch/arm/mpu/domain-page.c | 45 --
2 files changed, 1 insertion(+), 46 deletions(-)
delete mode 100644 xen/arc
Hi all,
This series is related to
"[PATCH 0/5] Third series for R82 MPU support". There is no build dependency
between the two series.
At the end of these 2 series, R82 and R52 boot till the same point
(approximately).
Kind regards,
Ayan
Ayan Kumar Halder (2):
arm/mpu: Enable is_xen_heap_page
On Thu, Aug 07, 2025 at 04:28:20PM +0200, Oleksii Kurochko wrote:
[..]
> Hi Arm/RISC-V maintainers,
>
> Do you foresee any need in bubbling up emulation_flags to the common `struct
> domain`?
>
>
> At the moment, in RISC-V's downstream branches emulation_flags isn't
> used. And,
> for n
On Wed, Aug 06, 2025 at 12:46:36PM +0200, Marek Marczykowski-Górecki wrote:
> On Wed, Aug 06, 2025 at 12:36:56PM +0200, Jan Beulich wrote:
> > On 06.08.2025 12:23, Marek Marczykowski-Górecki wrote:
> > > We've got several reports that S3 reliability recently regressed. We
> > > identified it's defi
On 05/08/2025 8:59 am, Jan Beulich wrote:
> While it is correct that in shim-exclusive mode log-dirty handling is
> all unreachable code, the present conditional still isn't correct: In a
> HVM=n and SHADOW_PAGING=n configuration log-dirty code also is all
> unreachable (and hence violating Misra r
On 8/6/25 10:12 AM, Jan Beulich wrote:
On 06.08.2025 09:45, Oleksii Kurochko wrote:
On 8/6/25 8:05 AM, Jan Beulich wrote:
Overall: There are very many items on this list, and it seems entirely clear to
me that not all of them will make it. I think it would be quite helpful to strip
down the se
On 07.08.2025 15:35, Oleksii Kurochko wrote:
>
> On 8/5/25 12:43 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> +static int p2m_alloc_root_table(struct p2m_domain *p2m)
>>> +{
>>> +struct domain *d = p2m->domain;
>>> +struct page_info *page;
>>> +const unsig
Hi Oleksii,
> On 5 Aug 2025, at 19:19, Oleksii Kurochko wrote:
>
> Hello everyone,
>
> This email only tracks big items for xen.git tree. Please reply for items you
> would like to see in 4.21 so that people have an idea what is going on and
> prioritise accordingly.
>
> You're welcome to prov
Hi Oleksii,
On 05.08.25 21:19, Oleksii Kurochko wrote:
> Hello everyone,
>
> This email only tracks big items for xen.git tree. Please reply for
> items you
> would like to see in 4.21 so that people have an idea what is going on and
> prioritise accordingly.
>
> You're welcome to provide descr
There are systems where device tree binary is passed by the U-Boot as
$fdtcontroladdr. In such cases, no external device tree binary is provided
during uboot script generation.
This is an enhancement on top of the following commit:-
uboot-script-gen: Dynamically compute addr and size when loading
On 07.08.2025 17:59, Oleksii Kurochko wrote:
> On 8/7/25 5:30 PM, Jan Beulich wrote:
>> On 07.08.2025 14:00, Oleksii Kurochko wrote:
>>> On 8/5/25 12:37 PM, Jan Beulich wrote:
On 31.07.2025 17:58, Oleksii Kurochko wrote:
> +/*
> + * Return back nr_root_pages to assure the root
On 8/7/25 5:30 PM, Jan Beulich wrote:
On 07.08.2025 14:00, Oleksii Kurochko wrote:
On 8/5/25 12:37 PM, Jan Beulich wrote:
On 31.07.2025 17:58, Oleksii Kurochko wrote:
+/*
+ * Return back nr_root_pages to assure the root table memory is also
+ * accounted against the P2M pool of th
On 8/4/25 4:16 PM, Jan Beulich wrote:
On 31.07.2025 17:58, Oleksii Kurochko wrote:
- Extended p2m_type_t with additional types: p2m_mmio_direct,
p2m_grant_map_{rw,ro}.
- Added macros to classify memory types: P2M_RAM_TYPES, P2M_GRANT_TYPES.
- Introduced helper predicates: p2m_is_ram(), p2m_i
On 07.08.2025 14:00, Oleksii Kurochko wrote:
> On 8/5/25 12:37 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> +/*
>>> + * Return back nr_root_pages to assure the root table memory is also
>>> + * accounted against the P2M pool of the domain.
>>> + */
>>>
On 8/4/25 4:11 PM, Jan Beulich wrote:
On 31.07.2025 17:58, Oleksii Kurochko wrote:
Rename `p2m_mmio_direct_dev` to a more architecture-neutral alias
`p2m_mmio_direct` to avoid leaking Arm-specific naming into common Xen code,
such as dom0less passthrough property handling.
This helps reduce pl
On 05/08/2025 21:19, Oleksii Kurochko wrote:
> Hello everyone,
>
> This email only tracks big items for xen.git tree. Please reply for
> items you
> would like to see in 4.21 so that people have an idea what is going on
> and
> prioritise accordingly.
>
> You're welcome to provide description and
On 8/7/25 12:11 PM, Jan Beulich wrote:
+unsigned long old;
+
+/* Figure-out number of VMID bits in HW */
+old = csr_read(CSR_HGATP);
+
+csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
+vmid_bits = csr_read(CSR_HGATP);
+vmid_bits = MASK_EXTR(vmid_bits, HGATP_VMID_MASK);
Nit
On 04.08.25 14:42, Leon Romanovsky wrote:
From: Leon Romanovsky
General dma_direct_map_resource() is going to be removed
in next patch, so simply open-code it in xen driver.
Signed-off-by: Leon Romanovsky
Reviewed-by: Juergen Gross
Juergen
OpenPGP_0xB0DE9DD628BF132F.asc
Description: Op
On 8/7/25 2:50 PM, Mykola Kvach wrote:
Hi Oleksii,
Hello Mykola,
=== ARM ===
* [4.21?] MPU mm subsistem skeleton
- Luca Fancellu
-
https://lore.kernel.org/xen-devel/20250312135258.1815706-1-luca.fance...@arm.com/
-https://patchew.org/Xen/20250312135258.1815706-1-luca.fance...@a
On 8/5/25 2:54 AM, dm...@proton.me wrote:
+ Cc: Oleskii
On Mon, Aug 04, 2025 at 11:46:36AM +0200, Jan Beulich wrote:
On 31.07.2025 21:21,dm...@proton.me wrote:
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -652,6 +652,8 @@ struct domain
unsigned int *llc_colors;
#endi
On Mon, Aug 04, 2025 at 03:42:34PM +0300, Leon Romanovsky wrote:
> Changelog:
> v1:
> * Added new DMA_ATTR_MMIO attribute to indicate
>PCI_P2PDMA_MAP_THRU_HOST_BRIDGE path.
> * Rewrote dma_map_* functions to use thus new attribute
> v0: https://lore.kernel.org/all/cover.1750854543.git.l...@ke
The function returning zero is an error indication; we shouldn't try to
map MFN 0 and then treat that page as a context table.
Signed-off-by: Jan Beulich
---
Whether to really have the ASSERT_UNREACHABLE() on the unmap path I'm
not quite sure about: According to my checking, the early bailing fro
On Mon, Aug 04, 2025 at 03:42:50PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky
>
> Block layer maps MMIO memory through dma_map_phys() interface
> with help of DMA_ATTR_MMIO attribute. There is a need to unmap
> that memory with the appropriate unmap function.
Be specific, AFIACT the i
On Mon, Aug 04, 2025 at 03:42:45PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky
>
> Introduce new DMA mapping functions dma_map_phys() and dma_unmap_phys()
> that operate directly on physical addresses instead of page+offset
> parameters. This provides a more efficient interface for driv
On 8/5/25 12:43 PM, Jan Beulich wrote:
On 31.07.2025 17:58, Oleksii Kurochko wrote:
+static int p2m_alloc_root_table(struct p2m_domain *p2m)
+{
+struct domain *d = p2m->domain;
+struct page_info *page;
+const unsigned int nr_root_pages = P2M_ROOT_PAGES;
+
+/*
+ * Return back
On Mon, Aug 04, 2025 at 03:42:47PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky
>
> In case peer-to-peer transaction traverses through host bridge,
> the IOMMU needs to have IOMMU_MMIO flag, together with skip of
> CPU sync.
>
> The latter was handled by provided DMA_ATTR_SKIP_CPU_SYNC
On Mon, Aug 04, 2025 at 03:42:46PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky
>
> Convert HMM DMA operations from the legacy page-based API to the new
> physical address-based dma_map_phys() and dma_unmap_phys() functions.
> This demonstrates the preferred approach for new code that sh
The do_IRQ() function is the main handler for processing IRQs.
Currently, due to restrictive checks, it does not process interrupt
numbers greater than 1024. This patch updates the condition to allow
the handling of interrupts from the eSPI range.
Signed-off-by: Leonid Komarianskyi
---
Changes i
Hello everyone!
### Background
Unlike the Linux kernel, which has supported extended shared peripheral
interrupts (eSPIs) since 2019 [1], Xen currently lacks support for this
interrupt range. For SoCs with GICv3.1+, this feature may be essential
because critical devices, such as consoles required
On Mon, Aug 04, 2025 at 03:42:41PM +0300, Leon Romanovsky wrote:
> --- a/kernel/dma/direct.h
> +++ b/kernel/dma/direct.h
> @@ -80,42 +80,54 @@ static inline void dma_direct_sync_single_for_cpu(struct
> device *dev,
> arch_dma_mark_clean(paddr, size);
> }
>
> -static inline dma_add
On Mon, Aug 04, 2025 at 03:42:43PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky
>
> Extend base DMA page API to handle MMIO flow.
I would mention here this follows the long ago agreement that we don't
need to enable P2P in the legacy dma_ops area. Simply failing when
getting an ATTR_MMI
Hi Oleksii,
On Tue, Aug 5, 2025 at 9:19 PM Oleksii Kurochko
wrote:
>
> Hello everyone,
>
> This email only tracks big items for xen.git tree. Please reply for
> items you
> would like to see in 4.21 so that people have an idea what is going on and
> prioritise accordingly.
>
> You're welcome to p
This change introduces resource management in the VGIC to handle
extended SPIs introduced in GICv3.1. The pending_irqs and
allocated_irqs arrays are resized to support the required
number of eSPIs, based on what is supported by the hardware and
requested by the guest. A new field, ext_shared_irqs,
Implemented support for GICv3.1 extended SPI registers for vGICv3,
allowing the emulation of eSPI-specific behavior for guest domains.
The implementation includes read and write emulation for eSPI-related
registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
following a similar approach t
Introduced two new helper functions: gic_is_valid_irq and
gic_is_shared_irq. The first function helps determine whether an IRQ
number is less than the number of lines supported by hardware. The
second function additionally checks if the IRQ number falls within the
SPI range. Also, updated the appro
To properly deactivate guest interrupts and allow them to be retriggered
after the initial trigger, the LR needs to be updated. The current
implementation ignores interrupts outside the range specified by the mask
0x3FF, which only covers IRQ numbers up to 1023. To enable processing of
eSPI interru
Currently, Xen does not support eSPI interrupts, leading
to a data abort when such interrupts are defined in the DTS.
This patch introduces a separate array to initialize up to
1024 interrupt descriptors in the eSPI range and adds the
necessary defines and helper function. These changes lay the
gr
Introduced appropriate register definitions, helper macros,
and initialization of required GICv3.1 distributor registers
to support eSPI. This type of interrupt is handled in the
same way as regular SPI interrupts, with the following
differences:
1) eSPIs can have up to 1024 interrupts, starting f
Currently, many common functions perform the same operations to calculate
GIC register addresses. This patch consolidates the similar code into
a separate helper function to improve maintainability and reduce duplication.
This refactoring also simplifies the implementation of eSPI support in future
The Dom0 configuration logic in create_dom0() has been updated
to account for extended SPIs when supported by the hardware and
enabled with CONFIG_GICV3_ESPI. These changes ensure the proper
calculation of the maximum number of SPIs and eSPIs available for Dom0.
When eSPIs are supported by the har
Introduced two new helper functions for vGIC: vgic_is_valid_irq and
vgic_is_shared_irq. The functions are similar to the newly introduced
gic_is_valid_irq and gic_is_shared_irq, but they verify whether a vIRQ
is available for a specific domain, while GIC-specific functions
validate INTIDs for the r
On Mon, Aug 04, 2025 at 03:42:42PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky
>
> Convert the KMSAN DMA handling function from page-based to physical
> address-based interface.
>
> The refactoring renames kmsan_handle_dma() parameters from accepting
> (struct page *page, size_t offset
On Mon, Aug 04, 2025 at 03:42:40PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky
>
> Combine iommu_dma_*map_phys with iommu_dma_*map_resource interfaces in
> order to allow single phys_addr_t flow.
Some later patch deletes iommu_dma_map_resource() ? Mention that plan here?
> --- a/drive
On 8/5/25 12:37 PM, Jan Beulich wrote:
On 31.07.2025 17:58, Oleksii Kurochko wrote:
Introduce support for allocating and initializing the root page table
required for RISC-V stage-2 address translation.
To implement root page table allocation the following is introduced:
- p2m_get_clean_page()
In order to support FRED, we're going to have to remove the {ds..gs} fields
from struct cpu_user_regs. This will impact v->arch.user_regs.
These fields are unused for HVM guests, but for PV hold the selector values
when the vCPU is scheduled out.
Introduce new fields for the selectors in struct
This is the next chunk of work in order to support FRED. Half of v1 is
already committed.
https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1972002392
Andrew Cooper (4):
x86/domctl: Stop using XLAT_cpu_user_regs()
x86/pv: Store the data segment selectors outside of cpu_user_reg
In order to support FRED, we're going to have to remove the {ds..gs} fields
from struct cpu_user_regs, meaning that it is going to have to become a
different type to the structure embedded in vcpu_guest_context_u.
In both arch_{get,set}_info_guest(), expand the memcpy()/XLAT_cpu_user_regs()
to cop
The data segment registers are part of the on-stack IRET frame when
interrupting Virtual 8086 mode, but this ceased being relevant for Xen in
commit 5d1181a5ea5e ("xen: Remove x86_32 build target.") in 2012.
With all other cleanup in place, delete the fields so we can introduce FRED
support which
In order to support FRED, we're going to have to remove the {ds..gs} fields
from struct cpu_user_regs, meaning that it is going to have to become a
different type to the structure embedded in vcpu_guest_context_u.
struct cpu_user_regs is a name used in common Xen code (i.e. needs to stay
using thi
On 07.08.2025 12:17, Andrew Cooper wrote:
> On 07/08/2025 10:30 am, Jan Beulich wrote:
>> On 06.08.2025 18:55, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/domctl.c
>>> +++ b/xen/arch/x86/domctl.c
>>> @@ -372,6 +372,14 @@ long arch_do_domctl(
>>> struct page_info *page;
>>> void *h
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