Hi Thomas,
On Wed, Aug 26, 2020 at 01:16:28PM +0200, Thomas Gleixner wrote:
[...]
>
> The whole lot is also available from git:
>
>git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git device-msi
>
> This has been tested on Intel/AMD/KVM but lacks testing on:
>
> - HYPERV
Hi Thomas,
I hit a compiler error while I was trying to compile this patchset:
arch/x86/kernel/devicetree.c: In function ‘dt_irqdomain_alloc’:
arch/x86/kernel/devicetree.c:232:6: error: ‘struct irq_alloc_info’ has no
member named ‘ioapic_id’; did you mean ‘ioapic’?
232 | tmp.ioapic_id =
On Fri, Jan 24, 2020 at 10:24:44AM +, Vincenzo Frascino wrote:
> Hi Boqun Feng,
>
> On 24/01/2020 06:32, Boqun Feng wrote:
> > Hi Vincenzo,
> >
>
> [...]
>
> >>
> >> I had a look to your patches and overall, I could not understand why we
&
Hi Vincenzo,
On Thu, Jan 23, 2020 at 10:48:07AM +, Vincenzo Frascino wrote:
> Hi Boqun Feng,
>
> sorry for the late reply.
>
That's OK, thanks for your review ;-)
> On 16/12/2019 00:19, Boqun Feng wrote:
> > Hi,
> >
> > This is the RFC patchset for vD
On Tue, Dec 17, 2019 at 03:10:16PM +0100, Vitaly Kuznetsov wrote:
> Boqun Feng writes:
>
> > Similar to x86, add a new vclock_mode VCLOCK_HVCLOCK, and reuse the
> > hv_read_tsc_page() for userspace to read tsc page clocksource.
> >
> > Signed-off-by: Boqun Feng
Since reading hyperv-timer clocksource requires reading cntvct,
userspace should be allowed to read it, otherwise reading cntvct will
result in traps, which makes vsyscall's cost similar compared to
syscall's.
So enable it on every cpu when a Hyper-V guest booting up.
Signed-off-by: Boqun Feng
Hi,
This is the RFC patchset for vDSO support in ARM64 Hyper-V guest. To
test it, Michael's ARM64 support patchset:
https://lore.kernel.org/linux-arm-kernel/1570129355-16005-1-git-send-email-mikel...@microsoft.com/
is needed.
Similar as x86, Hyper-V on ARM64 use a TSC page for guests
Similar to x86, add a new vclock_mode VCLOCK_HVCLOCK, and reuse the
hv_read_tsc_page() for userspace to read tsc page clocksource.
Signed-off-by: Boqun Feng (Microsoft)
---
arch/arm64/include/asm/clocksource.h | 3 ++-
arch/arm64/include/asm/mshyperv.h | 2 +-
arch/arm64
set-up in __vdso_init() to do this.
Note: if HYPERV_TIMER=y but the kernel is using other clocksource or
doesn't have the hyperv timer clocksource, tsc page will still be mapped
into userspace.
Signed-off-by: Boqun Feng (Microsoft)
---
arch/arm64/kernel/vdso.c | 12
arch
at userspace need to
be adjusted with some data from a page maintained by the hypervisor. For
example, the TSC page in Hyper-V.
This is a prerequisite for vDSO support in ARM64 on Hyper-V.
Signed-off-by: Boqun Feng (Microsoft)
---
arch/arm64/kernel/vdso.c | 43
1
driver and require arch_clocksource_data having
the same field.
Signed-off-by: Boqun Feng (Microsoft)
---
arch/arm/include/asm/clocksource.h| 6 +-
arch/arm/kernel/vdso.c| 1 -
arch/arm64/include/asm/clocksource.h | 6 +-
arch/arm64
initialized (using a kernel address) by the arch timer
driver, therefore not usable in vDSO.
Fix this by allowing a previous definition to override the default one,
so that in vDSO code, we can define it as a function callable in
userspace.
Signed-off-by: Boqun Feng (Microsoft)
---
arch/arm64
On Mon, Dec 04, 2017 at 08:15:11AM +0800, Boqun Feng wrote:
> Hi all,
>
> This is the v2 of RFC SGX Virtualization design and draft patches, you
Ping ;-)
Any comments?
Regards,
Boqun
> can find v1 at:
>
> https://lists.gt.net/xen/devel/483404
>
> In the new ver
From: Kai Huang
In libxc, a new structure 'xc_cpuid_policy_build_info_t' is added to carry
domain's EPC base and size info from libxl. libxl_cpuid_apply_policy is also
changed to take 'libxl_domain_build_info_t' as parameter, where domain's EPC
base and size can be got
with its value, and later on the vcpu's virtual IA32_SGXLEPUBKEYHASHn
will be set with the same value.
If the physical IA32_SGXLEPUBKEYHASHn MSRs are not writable, using
'lehash' or 'lewr' parameter results in domain creation failure.
Signed-off-by: Boqun Feng <boqun.f...@intel.com>
---
tools
cache the recent IA32_SGXLEPUBKEYHASHn in a
percpu variable, so that we won't need to update with wrmsr if the value
not changed.
Signed-off-by: Kai Huang <kai.hu...@linux.intel.com>
Signed-off-by: Boqun Feng <boqun.f...@intel.com>
---
xen/arch/x86/domctl.c| 28 -
xe
ed-off-by: Kai Huang <kai.hu...@linux.intel.com>
Signed-off-by: Boqun Feng <boqun.f...@intel.com>
---
xen/arch/x86/mm.c| 9 +++--
xen/include/asm-x86/mm.h | 7 +++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c
From: Kai Huang
Currently EPC are statically allocated and mapped to guest, we don't have
to trap ENCLS as it runs perfectly in VMX non-root mode. But exposing SGX
to guest means we also expose ENABLE_ENCLS bit to L1 hypervisor, therefore
we cannot stop L1 from
need to do is to populate the portion of EPC pages in
the 'frame_table' and set up the mapping properly.
SGX would be disabled, if EPC initialization found any problem.
Signed-off-by: Boqun Feng <boqun.f...@intel.com>
---
xen/arch/x86/sgx.c
From: Kai Huang
A new 'p2m_epc' type is added for EPC mapping type. Two wrapper functions
set_epc_p2m_entry and clear_epc_p2m_entry are also added for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/p2m-ept.c | 3 +++
https://01.org/intel-software-guard-extensions
- Linux SGX driver for upstreaming
https://github.com/01org/linux-sgx
- Intel SGX Specification (SDM Vol 3D)
https://software.intel.com/sites/default/files/managed/7c/f1/332831-sdm-vol-3d.pdf
- Paper: Intel SGX Explained
htt
tel.com>
Signed-off-by: Boqun Feng <boqun.f...@intel.com>
---
xen/arch/x86/hvm/vmx/vmx.c | 3 +
xen/arch/x86/sgx.c | 340 +
xen/include/asm-x86/hvm/vmx/vmcs.h | 2 +
xen/include/asm-x86/sgx.h | 13 ++
4 files changed
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