in code parts that require cache maintenance).
Signed-off-by: Dmytro Firsov
Reviewed-by: Julien Grall
Tested-by: Mykola Kvach
---
v2:
- changed comment for non_coherent struct member
- added Julien's RB
- added Mykola's TB
---
xen/drivers/passthrough/arm/s
Hi Julien, Michal
On 28.08.25 00:42, Julien Grall wrote:
> Hi Michal,
>
> On 26/08/2025 12:44, Orzel, Michal wrote:
>>
>>
>> On 26/08/2025 12:48, Julien Grall wrote:
>>> Hi,
>>>
>>> On 26/08/2025 10:47, Dmytro Firsov wrote:
>>>> O
Hi Michal,
On 22.08.25 11:12, Orzel, Michal wrote:
On 06/08/2025 16:58, Dmytro Firsov wrote:
According to the Arm SMMUv3 spec (ARM IHI 0070), a system may have
SMMU(s) that is/are non-coherent to the PE (processing element). In such
cases, memory accesses from the PE should be either non
in code parts that require cache maintenance).
Signed-off-by: Dmytro Firsov
---
xen/drivers/passthrough/arm/smmu-v3.c | 27 +++
xen/drivers/passthrough/arm/smmu-v3.h | 7 +++
2 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/xen/drivers/passthrough/arm/s
an existing user of uImage
>> (maybe EPAM or Arm?) to confirm they are happy with the change.
>
> I have just re-checked current patch in our typical Xen based
> environment (no dom0less, Linux in Dom0) and didn't notice issues with
> it. But we use zImage for Dom0's
