RE: [PATCH v1 7/7] x86/vmx: switch IPT MSRs on vmentry/vmexit

> > On Wed, Jun 17, 2020 at 01:54:45PM +0200, Michał Leszczyński wrote: > >> - 17 cze 2020 o 11:09, Roger Pau Monné roger@citrix.com napisał(a): > >> > >>> 24 Virtual Machine Control Structures -> 24.8 VM-entry Control > >>> Fields -> 24.8.1 VM-Entry Controls Software should consult the

RE: [PATCH v1 0/7] Implement support for external IPT monitoring

> > > How does KVM deal with this, do they insert/modify trace packets on > > > trapped and emulated instructions by the VMM? > > > > The KVM includes instruction decoder and > emulator(arch/x86/kvm/emulate.c), and the guest's memory can be set to > write-protect as well. But it doesn't support

RE: [PATCH v1 0/7] Implement support for external IPT monitoring

> ; Nakajima, Jun ; > > > George Dunlap ; Ian Jackson > > > ; Julien Grall ; Stefano > > > Stabellini ; Kang, Luwei > > > > > > Subject: RE: [PATCH v1 0/7] Implement support for external IPT > > > monitoring > > > > > > +Lu

RE: [PATCH v1 0/7] Implement support for external IPT monitoring

> -Original Message- > From: Tian, Kevin > Sent: Wednesday, June 17, 2020 9:35 AM > To: Michał Leszczyński ; Andrew Cooper > > Cc: Xen-devel ; Jan Beulich > ; Wei Liu ; Roger Pau Monné > ; Nakajima, Jun ; George > Dunlap ; Ian Jackson ; > Julien Grall ; Stef

Re: [Xen-devel] x86 Community Call - Wed July 11, 14:00 - 15:00 UTC - Minutes

Hi Lars, I think I have sent the minutes of design session to you. I attached the email in case you can’t found. Thanks, Luwei Kang From: Lars Kurth [mailto:lars.ku...@citrix.com] Sent: Thursday, July 12, 2018 9:23 PM To: Ji, John ; xen-devel Cc: committ...@xenproject.org; Tamas K Lengyel ;

Re: [Xen-devel] [PATCH v2 03/10] x86: Add Intel Processor Trace support for cpuid

> >>> On 30.05.18 at 15:27, wrote: > > @@ -759,12 +760,19 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t > > domid, > > continue; > > } > > > > +if ( input[0] == 0x14 ) > > +{ > > +input[1]++; > > +if ( input[1] == 1 ) >

Re: [Xen-devel] [PATCH v2 06/10] x86: Introduce a new function to get capability of Intel PT

> >> >> > +#define IPT_CAP(_n, _l, _r, _m) \ > >> >> > +[IPT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \ > >> >> > +.reg = _r, .mask = _m } > >> >> > + > >> >> > +static struct ipt_cap_desc { > >> >> > +const char*name; > >> >> > +

Re: [Xen-devel] [PATCH v2 05/10] x86: Implement Intel Processor Trace context switch

> >> >> > @@ -40,3 +42,102 @@ static int __init parse_ipt_params(const > >> >> > char > >> >> > +static inline void ipt_save_msr(struct ipt_ctx *ctx, unsigned > >> >> > +int > >> >> > +addr_range) { > >> >> > +unsigned int i; > >> >> > + > >> >> > +rdmsrl(MSR_IA32_RTIT_STATUS,

Re: [Xen-devel] [PATCH v2 05/10] x86: Implement Intel Processor Trace context switch

> >> > @@ -40,3 +42,102 @@ static int __init parse_ipt_params(const char > >> > +static inline void ipt_save_msr(struct ipt_ctx *ctx, unsigned int > >> > +addr_range) { > >> > +unsigned int i; > >> > + > >> > +rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); > >> > +

Re: [Xen-devel] [PATCH v2 06/10] x86: Introduce a new function to get capability of Intel PT

> >> > +#define IPT_CAP(_n, _l, _r, _m) \ > >> > +[IPT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \ > >> > +.reg = _r, .mask = _m } > >> > + > >> > +static struct ipt_cap_desc { > >> > +const char*name; > >> > +unsigned int leaf; >

Re: [Xen-devel] [PATCH v2 08/10] x86: Introduce a function to check the value of RTIT_CTL

> > Any attempt to modify IA32_RTIT_CTL while TraceEn is set will result > > in a #GP unless the same write also clears TraceEn. > > Writes to IA32_RTIT_CTL that do not modify any bits will not cause a > > #GP, even if TraceEn remains set. > > MSR write that attempts to change bits marked

Re: [Xen-devel] [PATCH v2 09/10] x86: Disable Intel Processor Trace when VMXON in L1 guest

> > @@ -1519,6 +1520,14 @@ int nvmx_handle_vmxon(struct cpu_user_regs *regs) > > v->arch.hvm_vmx.launched = 0; > > vmsucceed(regs); > > > > +if ( v->arch.hvm_vmx.ipt_desc ) > > +{ > > +v->arch.hvm_vmx.ipt_desc->ipt_guest.ctl = 0; > > +vmx_vmcs_enter(current); > >

Re: [Xen-devel] [PATCH v2 01/10] x86: add an flag to enable Intel Processor Trace in guest

> > --- a/docs/misc/xen-command-line.markdown > > +++ b/docs/misc/xen-command-line.markdown > > @@ -1215,6 +1215,16 @@ Rather than only mapping RAM pages for IOMMU > > accesses for Dom0, with this option all pages not marked as unusable > > in the E820 table will get a mapping established. > > >

Re: [Xen-devel] [PATCH v2 05/10] x86: Implement Intel Processor Trace context switch

> > @@ -40,3 +42,102 @@ static int __init parse_ipt_params(const char > > *str) > > > > return 0; > > } > > + > > +static inline void ipt_load_msr(const struct ipt_ctx *ctx, > > + unsigned int addr_range) > > Please let the compiler decide whether to inline such

Re: [Xen-devel] [PATCH v2 04/10] x86: Add Intel Processor Trace MSRs and bit definitions

> > --- a/xen/include/asm-x86/msr-index.h > > +++ b/xen/include/asm-x86/msr-index.h > > @@ -548,4 +548,41 @@ > > #define MSR_PKGC9_IRTL 0x0634 > > #define MSR_PKGC10_IRTL0x0635 > > > > +/* Intel PT MSRs */ > > +#define MSR_IA32_RTIT_CTL

Re: [Xen-devel] [PATCH v2 03/10] x86: Add Intel Processor Trace support for cpuid

> > --- a/xen/include/public/arch-x86/cpufeatureset.h > > +++ b/xen/include/public/arch-x86/cpufeatureset.h > > @@ -215,6 +215,7 @@ XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor > > Mode Access Prevention */ > > XEN_CPUFEATURE(AVX512IFMA,5*32+21) /*A AVX-512 Integer Fused Multiply

Re: [Xen-devel] [PATCH v2 07/10] x86: Add Intel Processor Trace MSRs read/write emulation

> > --- a/xen/arch/x86/hvm/vmx/vmx.c > > +++ b/xen/arch/x86/hvm/vmx/vmx.c > > @@ -2898,6 +2898,15 @@ static int vmx_msr_read_intercept(unsigned int > > msr, uint64_t *msr_content) > > if ( vpmu_do_rdmsr(msr, msr_content) ) > > goto gp_fault; > > break; > > +case

Re: [Xen-devel] [PATCH v2 06/10] x86: Introduce a new function to get capability of Intel PT

> > --- a/xen/arch/x86/cpu/ipt.c > > +++ b/xen/arch/x86/cpu/ipt.c > > @@ -25,11 +25,74 @@ > > #include > > #include > > > > +#define EAX 0 > > +#define ECX 1 > > +#define EDX 2 > > +#define EBX 3 > > +#define CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */ > > + > > +#define

Re: [Xen-devel] [PATCH v2 00/10] Intel Processor Trace virtulization enabling

> >> -Original Message- > >> From: Julien Grall [mailto:julien.gr...@arm.com] > >> Sent: Wednesday, May 30, 2018 11:15 PM > >> To: Kang, Luwei ; xen-de...@lists.xen.org > >> Cc: andrew.coop...@citrix.com; george.dun...@eu.citrix.com; >

Re: [Xen-devel] [PATCH v2 00/10] Intel Processor Trace virtulization enabling

> -Original Message- > From: Julien Grall [mailto:julien.gr...@arm.com] > Sent: Wednesday, May 30, 2018 11:15 PM > To: Kang, Luwei ; xen-de...@lists.xen.org > Cc: andrew.coop...@citrix.com; george.dun...@eu.citrix.com; > ian.jack...@eu.citrix.com; jbeul...@su

Re: [Xen-devel] [PATCH RESEND v1 0/7] Intel Processor Trace virtulization enabling

> > Here is a patch-series which adding Processor Trace enabling in XEN > > guest. You can get It's software developer manuals from: > > https://software.intel.com/sites/default/files/managed/c5/15/archi > > te ct ure-instruction-set-extensions-programming-reference.pdf > > In

Re: [Xen-devel] [PATCH RESEND v1 0/7] Intel Processor Trace virtulization enabling

> >>> Here is a patch-series which adding Processor Trace enabling in XEN > >>> guest. You can get It's software developer manuals from: > >>> https://software.intel.com/sites/default/files/managed/c5/15/archite > >>> ct ure-instruction-set-extensions-programming-reference.pdf > >>> In Chapter 5

Re: [Xen-devel] [PATCH RESEND v1 6/7] x86: Implement Intel Processor Trace MSRs read/write

> >>> On 04.05.18 at 05:53, wrote: > >> > Thanks for your clarification. Please correct me if I have > >> > something wrong. Guest may execute an instruction and this > >> > instruction may produce an PT packet save in PT output buffer. An > >> > EPT violation will be

Re: [Xen-devel] [PATCH RESEND v1 0/7] Intel Processor Trace virtulization enabling

> > > > Here is a patch-series which adding Processor Trace enabling in XEN > > > > guest. You can get It's software developer manuals from: > > > > https://software.intel.com/sites/default/files/managed/c5/15/archi > > > > tect ure-instruction-set-extensions-programming-reference.pdf > > > > In

Re: [Xen-devel] [PATCH RESEND v1 6/7] x86: Implement Intel Processor Trace MSRs read/write

> > Thanks for your clarification. Please correct me if I have > > something wrong. Guest may execute an instruction and this instruction > > may produce an PT packet save in PT output buffer. An EPT violation > > will be generated if the address of this PT buffer don't have EPT page > >

Re: [Xen-devel] [PATCH RESEND v1 0/7] Intel Processor Trace virtulization enabling

> >>> Here is a patch-series which adding Processor Trace enabling in XEN > >>> guest. You can get It's software developer manuals from: > >>> https://software.intel.com/sites/default/files/managed/c5/15/archite > >>> ct ure-instruction-set-extensions-programming-reference.pdf > >>> In Chapter 5

Re: [Xen-devel] [PATCH RESEND v1 0/7] Intel Processor Trace virtulization enabling

> > Here is a patch-series which adding Processor Trace enabling in XEN guest. > > You can get It's software developer manuals from: > > https://software.intel.com/sites/default/files/managed/c5/15/architect > > ure-instruction-set-extensions-programming-reference.pdf > > In Chapter 5 INTEL

Re: [Xen-devel] [PATCH RESEND v1 6/7] x86: Implement Intel Processor Trace MSRs read/write

> >>> On 03.05.18 at 07:22, wrote: > >> And there is one more thing I've not found throughout the series: EPT > > violations and a few other VM exits have gained a new > >> qualification bit, indicating that it's not the current instruction > >> which > > has caused the

Re: [Xen-devel] [PATCH RESEND v1 6/7] x86: Implement Intel Processor Trace MSRs read/write

> > +int pt_do_wrmsr(unsigned int msr, uint64_t msr_content) { > > +struct pt_desc *pt_desc = >arch.hvm_vmx.pt_desc; > > + > > +if ( !opt_intel_pt ) > > +return 1; > > + > > +switch ( msr ) { > > +case MSR_IA32_RTIT_CTL: > > +pt_set_rtit_ctl(pt_desc, msr_content); >

Re: [Xen-devel] [PATCH RESEND v1 0/7] Intel Processor Trace virtulization enabling

> > Here is a patch-series which adding Processor Trace enabling in XEN guest. > > You can get It's software developer manuals from: > > https://software.intel.com/sites/default/files/managed/c5/15/architect > > ure-instruction-set-extensions-programming-reference.pdf > > In Chapter 5 INTEL

Re: [Xen-devel] [PATCH RESEND v1 2/7] x86: configure vmcs for Intel processor trace virtualization

> >> >>> On 28.04.18 at 03:07, wrote: > >> >> > @@ -383,13 +388,28 @@ static int vmx_init_vmcs_config(void) > >> >> > _vmx_secondary_exec_control &= > >> >> > ~SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS; > >> >> > > >> >> > min = 0; > >> >> > -opt =

Re: [Xen-devel] [PATCH RESEND v1 3/7] x86: add intel proecessor trace support for cpuid

> > This patch add Intel processor trace support for cpuid handling. > > The 0x14 usage screams of wanting an #define. Get it. Will define leaf 0x14 as a macro in next version. Thanks for the review. Luwei Kang ___ Xen-devel mailing list

Re: [Xen-devel] [PATCH RESEND v1 0/7] Intel Processor Trace virtulization enabling

> On Tue, Jan 16, 2018 at 02:12:26AM +0800, Luwei Kang wrote: > > Hi All, > > > > Here is a patch-series which adding Processor Trace enabling in XEN guest. > > You can get It's software developer manuals from: > > https://software.intel.com/sites/default/files/managed/c5/15/architect > >

Re: [Xen-devel] [PATCH RESEND v1 2/7] x86: configure vmcs for Intel processor trace virtualization

> >>> On 28.04.18 at 03:07, wrote: > >> > @@ -383,13 +388,28 @@ static int vmx_init_vmcs_config(void) > >> > _vmx_secondary_exec_control &= > >> > ~SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS; > >> > > >> > min = 0; > >> > -opt = VM_ENTRY_LOAD_GUEST_PAT |

Re: [Xen-devel] [PATCH RESEND v1 5/7] x86: Implement Intel Processor Trace context switch

> > --- a/xen/arch/x86/cpu/intel_pt.c > > +++ b/xen/arch/x86/cpu/intel_pt.c > > @@ -21,7 +21,76 @@ > > #include > > #include > > #include > > +#include > > +#include > > > > /* intel_pt: Flag to enable Intel Processor Trace (default on). */ > > bool_t __read_mostly opt_intel_pt = 1;

Re: [Xen-devel] [PATCH RESEND v1 4/7] x86: add intel processor trace context

> > --- a/xen/include/asm-x86/hvm/vmx/vmcs.h > > +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h > > @@ -20,6 +20,7 @@ > > > > #include > > #include > > +#include > > > > extern void vmcs_dump_vcpu(struct vcpu *v); extern void > > setup_vmcs_dump(void); @@ -171,6 +172,8 @@ struct arch_vmx_struct {

Re: [Xen-devel] [PATCH RESEND v1 2/7] x86: configure vmcs for Intel processor trace virtualization

> > This patch configure VMCS to make Intel PT output address can be treat > > as guest physical address and translated by EPT when intel_pt option > > is true. > > There have some constraint condition on VMCS configuration, otherwise > > will cause VM entry failed. > > > > 1. If the “Guest PT

Re: [Xen-devel] [PATCH RESEND v1 1/7] x86: add a flag to enable Intel processor trace

> >>> On 27.04.18 at 11:01, wrote: > >Thanks for you review. "ptrace" make me associate "strace", "ftrace". > > Although they are complete different things but I think "ptrace" is > > not good enough to present "Intel Processor Trace". > > Then how about ipt instead of

Re: [Xen-devel] [PATCH RESEND v1 1/7] x86: add a flag to enable Intel processor trace

> >>> On 27.04.18 at 10:22, wrote: > >> > diff --git a/docs/misc/xen-command-line.markdown > >> > b/docs/misc/xen-command-line.markdown > >> > index 781110d..95411cf 100644 > >> > --- a/docs/misc/xen-command-line.markdown > >> > +++ b/docs/misc/xen-command-line.markdown > >>

Re: [Xen-devel] [PATCH RESEND v1 1/7] x86: add a flag to enable Intel processor trace

> > --- a/docs/misc/xen-command-line.markdown > > +++ b/docs/misc/xen-command-line.markdown > > @@ -1009,6 +1009,13 @@ debug hypervisor only). > > ### idle\_latency\_factor > > > `= ` > > > > +### intel\_pt > > +> `= ` > > + > > +> Default: `true` > > + > > +Flag to enable Intel Processor Trace.

Re: [Xen-devel] [PATCH RESEND v1 5/7] x86: Implement Intel Processor Trace context switch

> > Load/Store Intel processor trace register in context switch. > > MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS. > > When Intel PT is supported in guest, we need load/restore PT MSRs only > > when PT is enabled in guest. > > > > Signed-off-by: Luwei Kang > >

Re: [Xen-devel] [PATCH RESEND v1 1/7] x86: add a flag to enable Intel processor trace

> > diff --git a/docs/misc/xen-command-line.markdown > > b/docs/misc/xen-command-line.markdown > > index 781110d..95411cf 100644 > > --- a/docs/misc/xen-command-line.markdown > > +++ b/docs/misc/xen-command-line.markdown > > @@ -1009,6 +1009,13 @@ debug hypervisor only). > > ###

Re: [Xen-devel] [PATCH RESEND v1 1/7] x86: add a flag to enable Intel processor trace

> > diff --git a/docs/misc/xen-command-line.markdown > > b/docs/misc/xen-command-line.markdown > > index 781110d..95411cf 100644 > > --- a/docs/misc/xen-command-line.markdown > > +++ b/docs/misc/xen-command-line.markdown > > @@ -1009,6 +1009,13 @@ debug hypervisor only). > > ###