Hi Oleksandr,
Oleksandr Tyshchenko writes:
[...]
>> +static inline uint32_t vgic_get_reg_offset(uint32_t reg, uint32_t spi_base,
>> + uint32_t espi_base)
>> +{
>> +if ( reg < espi_base )
>> +return reg - spi_base;
>> +else
>> +r
Hi,
Grygorii Strashko writes:
> On 27.08.25 03:16, Volodymyr Babchuk wrote:
>> Hi Grygorii,
>> Grygorii Strashko writes:
>>
>>> From: Grygorii Strashko
>>>
>>> Now Arm64 AArch32 guest support is always enabled and built-in while not
>>
Hi Grygorii,
Grygorii Strashko writes:
> On 27.08.25 03:22, Volodymyr Babchuk wrote:
>> Hi,
>> Grygorii Strashko writes:
>>
>>> From: Grygorii Strashko
>>>
>>> Split set_domain_type() between Arm64/Arm32 sub-arches as
>>> set_domai
ins unaffected when guests do not request
> eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
> option is disabled.
>
> Signed-off-by: Leonid Komarianskyi
> Reviewed-by: Oleksandr Tyshchenko
Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V7:
> - m
ion.
>
> Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V7:
> - fixed the condition in the is_espi assert for non-eSPI builds: the
> previous condition was mistakenly added with a wrong check and led to
> triggering asserts for all no
Hi Leonid,
Leonid Komarianskyi writes:
> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
> re
Hi Stefano,
Stefano Stabellini writes:
> Hi Oleksii,
>
> It is still not passing the ci-loop, this time due to MISRA. See the two
> new 8.3 and 8.4 violations (previously zero) and also new additional
> 12.2, 13.1 violations:
>
Is there any way to run this kind of tests locally? (I suppose that
only covers IRQ numbers up to 1023. To enable
> processing of eSPI interrupts, this patch updates the mask to 0x1FFF.
>
> Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V6:
> - updated mask to 0x1fff to avoid confusion
> - updated
r of ifdefs and code duplication in further changes
> - removed reviewed-by as moving defines from ifdefs requires additional
> confirmation from reviewers
>
> Changes in V4:
> - removed redundant line with 'default n' in Kconfig, as it is disabled
> by default, w
Hi Mykola,
Mykola Kvach writes:
> From: Mykola Kvach
>
> This is part 2 of version 5 of the ARM Xen system suspend/resume patch
> series, based on earlier work by Mirela Simonovic and Mykyta Poturai.
>
> The first part is here:
> https://marc.info/?l=xen-devel&m=175659181415965&w=2
>
> This v
gned-off-by: Mirela Simonovic
> Signed-off-by: Saeed Nowshadi
> Signed-off-by: Mykola Kvach
Reviewed-by: Volodymyr Babchuk
> ---
> Changes in V4:
> - Rephrased comment and commit message for better clarity
> - Created separate function for disabling physical timers
>
de and avoids intrusive changes to the generic resume flow.
>
> Usage:
>
> For Linux-based guests, suspend can be initiated with:
> echo mem > /sys/power/state
> or via:
> systemctl suspend
>
> Resuming the guest is performed from control domain using:
>
t;
> Signed-off-by: Oleksandr Tyshchenko
> Signed-off-by: Mykola Kvach
Reviewed-by: Volodymyr Babchuk
> ---
> Changes in V6:
> - Drop iommu_enabled check from host system suspend.
> ---
> xen/arch/arm/suspend.c| 11 +++
> xen/drivers/passthrough/ar
Hi,
Mykola Kvach writes:
> From: Oleksandr Tyshchenko
>
> Store and restore active context and micro-TLB registers.
>
> Tested on R-Car H3 Starter Kit.
>
> Signed-off-by: Oleksandr Tyshchenko
> Signed-off-by: Mykola Kvach
Reviewed-by: Volodymyr Babchuk
(except when only 1 PCPU is online).
> */
>
> This patch adds system state checks to guard calls to request_irq
> and release_irq. These calls are now skipped when system_state is
> SYS_STATE_{resume,suspend}, preventing unsafe operations during
> suspend/resume handling.
>
>
led by the hypervisor. Other GIC registers which are accessible
> by guests are saved/restored on context switch.
>
> Signed-off-by: Mirela Simonovic
> Signed-off-by: Saeed Nowshadi
> Signed-off-by: Mykyta Poturai
> Signed-off-by: Mykola Kvach
Reviewed-by: Volodymyr Babchuk
Hi Leonid,
Leonid Komarianskyi writes:
> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
>
on is disabled, the hardware does not support eSPIs, or the domain
> does not request such interrupts, the functionality remains unchanged.
>
> Signed-off-by: Leonid Komarianskyi
I have a couple of comments about coding style, but apart from that it
looks really good. Wi
requires additional
> confirmation from reviewers
>
> Changes in V4:
> - added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
> for vGIC emulation
> - added a log banner with eSPI information, similar to the one for
> regular SPI
> - added newline
- removed redundant line with 'default n' in Kconfig, as it is disabled
> by default, without explicit specification
> - added reviewed-by from Volodymyr Babchuk
>
> Changes in V3:
> - introduced a new define NR_ESPI_IRQS to avoid confusion, like in the
> case of using N
Hi Milan,
Thanks, "Security Considerations" sections looks really good. But I have
more questions.
Milan Djokic writes:
> Hello Julien, Volodymyr
>
> On 8/27/25 01:28, Volodymyr Babchuk wrote:
>> Hi Milan,
>> Milan Djokic writes:
>>
>>> Hello
de and avoids intrusive changes to the generic resume flow.
>
> Usage:
>
> For Linux-based guests, suspend can be initiated with:
> echo mem > /sys/power/state
> or via:
> systemctl suspend
>
> Resuming the guest is performed from control domain using:
>
Hi Mykola,
Mykola Kvach writes:
> From: Mykola Kvach
>
> Add support for the PSCI SYSTEM_SUSPEND function in the vPSCI interface,
> allowing guests to request suspend via the PSCI v1.0 SYSTEM_SUSPEND call
> (both 32-bit and 64-bit variants).
>
> Implementation details:
> - Add SYSTEM_SUSPEND fu
Hi Leonid,
Leonid Komarianskyi writes:
> Since eSPI support has been introduced, update the documentation with
> the appropriate description.
>
> Signed-off-by: Leonid Komarianskyi
>
> ---
> Changes in V4:
> - introduced this patch
> ---
> docs/man/xl.cfg.5.pod.in | 13 -
> 1 file
the
> calculation defaults to using the standard SPI range, with a maximum value of
> 992 interrupt lines, as it works currently.
>
> Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V4:
> - consolidated the eSPI and SPI logic into a
Hi Leonid,
Leonid Komarianskyi writes:
> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
> re
gister operations.
>
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
>
> Signed-off-by: Leonid Komarianskyi
> Reviewed-by: Volodymyr Babchuk
With latest changes:
Reviewed-by: Volodymyr
s, which replace open-coded checks
> with the use of these new helper functions, do not introduce any
> functional changes, as the helper functions follow the current vIRQ
> index verification logic.
>
> Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
>
Grygorii Strashko writes:
> From: Grygorii Strashko
>
> Split is_32bit/64bit_domain() macro implementations between arm64/arm32.
>
> Signed-off-by: Grygorii Strashko
Reviewed-by: Volodymyr Babchuk
> ---
> v2:
> - fix comments related to macro parameters evaluation
Hi,
Grygorii Strashko writes:
> From: Grygorii Strashko
>
> Split set_domain_type() between Arm64/Arm32 sub-arches as
> set_domain_type() implementation is going to be extended for Arm64.
>
> Signed-off-by: Grygorii Strashko
> ---
> v2:
> - no changes, rebase
>
> xen/arch/arm/arm32/Makefile
dec hex filename
> 859212322404 270880 1452496 1629d0 xen-syms-before
>
> After (CONFIG_ARM64_AARCH32=n):
>text data bss dec hex filename
> 851256322404 270880 1444540 160abc xen-syms-after
>
> Signed-off-by: Grygorii Strashko
R
Hi Grygorii,
Grygorii Strashko writes:
> From: Grygorii Strashko
>
> Now Arm64 AArch32 guest support is always enabled and built-in while not
> all Arm64 platforms supports AArch32 (for exmaple on Armv9A) or this
> support might not be needed (Arm64 AArch32 is used quite rarely in embedded
> sy
Hi Leonid,
Leonid Komarianskyi writes:
> Introduced two new helper functions for vGIC: vgic_is_valid_line and
> vgic_is_spi. The functions are similar to the newly introduced
> gic_is_valid_line and gic_is_spi, but they verify whether a vIRQ
> is available for a specific domain, while GIC-spe
Hi Milan,
Milan Djokic writes:
> Hello Julien,
>
> On 8/13/25 14:11, Julien Grall wrote:
>> On 13/08/2025 11:04, Milan Djokic wrote:
>>> Hello Julien,
>> Hi Milan,
>>
>>>
>>> We have prepared a design document and it will be part of the updated
>>> patch series (added in docs/design). I'll als
gister operations.
>
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
>
> Signed-off-by: Leonid Komarianskyi
With nit fixed:
Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V2:
> - mo
Hi Leonid,
Leonid Komarianskyi writes:
> The Dom0 and DomUs logic for the dom0less configuration in create_dom0()
> and arch_create_domUs() has been updated to account for extended SPIs
> when supported by the hardware and enabled with CONFIG_GICV3_ESPI. These
> changes ensure the proper calcula
Hi Leonid,
Leonid Komarianskyi writes:
> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
>
errupt
> numbers greater than 1024. This patch updates the condition to allow
But check reads "irq < 1020"...
> the handling of interrupts from the eSPI range.
>
With commit message fixed:
Reviewed-by: Volodymyr Babchuk
> Signed-off-by: Leonid Komarianskyi
>
> ---
> C
umbers up to 1023. To enable processing of
> eSPI interrupts, this patch updates the mask to 0x13FF.
>
> Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V2:
> - remove unnecessary CONFIG_GICV3_ESPI ifdef guard
>
> Changes in V
ion.
>
> Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V2:
> - use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
> - remove unnecessary comment for nr_irqs initialization
>
> Changes in V3:
> - introduced a new def
ctoring also simplifies the implementation of eSPI support in future
> changes.
>
> Signed-off-by: Leonid Komarianskyi
> Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V2:
> - no changes
>
> Changes in V3:
> - changed panic() in get_addr_by_offset() to printing w
Hello, sorry for the noise,
But I noticed small nick when reviewing next patch, which is very similar.
Volodymyr Babchuk writes:
> Leonid Komarianskyi writes:
>
>> Introduced two new helper functions: gic_is_valid_line and
>> gic_is_spi. The first function helps determ
elper functions, do not introduce any functional changes, as the helper
> functions follow the current IRQ index verification logic.
>
> Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V2:
> - introduced this patch
>
> Ch
Hi,
Mykola Kvach writes:
> From: Oleksandr Tyshchenko
>
> This is done using generic iommu_suspend/resume functions that cause
> IOMMU driver specific suspend/resume handlers to be called for enabled
> IOMMU (if one has suspend/resume driver handlers implemented).
>
> These handlers work only w
Hi Mykola,
Mykola Kvach writes:
> From: Oleksandr Tyshchenko
>
> Store and restore active context and micro-TLB registers.
>
> Tested on R-Car H3 Starter Kit.
>
> Signed-off-by: Oleksandr Tyshchenko
> Signed-off-by: Mykola Kvach
> ---
> xen/drivers/passthrough/arm/ipmmu-vmsa.c | 269 ++
Hi Mykola,
Mykola Kvach writes:
> From: Mirela Simonovic
>
> The context of CPU general purpose and system control registers
> has to be saved on suspend and restored on resume. This is
> implemented in hyp_suspend and before the return from hyp_resume
> function. The hyp_suspend is invoked j
Hi Mykola,
Sequence of next 3 patches (and previous one) really puzzles me. Can you
first implement hyp_resume() function, then add PSCI_SYSTEM_SUSPEND call
and only then implement system_suspend() function? Why do this backwards?
Mykola Kvach writes:
> From: Mirela Simonovic
>
> Invoke PSCI
Hi Mykola,
Mykola Kvach writes:
> From: Mirela Simonovic
>
> Trigger Xen suspend when the hardware domain initiates suspend via
> SHUTDOWN_suspend. Redirect system suspend to CPU#0 to ensure the
> suspend logic runs on the boot CPU, as required.
>
> Introduce full suspend/resume infrastructure
Hi Jan,
Jan Beulich writes:
> On 11.08.2025 22:48, Mykola Kvach wrote:
>> --- a/xen/common/domain.c
>> +++ b/xen/common/domain.c
>> @@ -1311,7 +1311,11 @@ int domain_shutdown(struct domain *d, u8 reason)
>> d->shutdown_code = reason;
>> reason = d->shutdown_code;
>>
>> +#if defin
Hi Mykola,
Mykola Kvach writes:
> From: Mykola Kvach
>
> On ARM, the first 32 interrupts (SGIs and PPIs) are banked per-CPU
> and not restored by gic_resume (for secondary cpus).
>
> This patch introduces restore_local_irqs_on_resume, a function that
> restores the state of local interrupts on
ve banked IRQ descs state during resume.
>
> Signed-off-by: Mykola Kvach
Reviewed-by: Volodymyr Babchuk
> ---
> xen/arch/arm/irq.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 4bbf0b0664..148f184f
Hi Mykola,
Mykola Kvach writes:
While I approve the change, the commit message is somewhat
unclear. Maybe "Don't release IRQs on suspend" will be better?
> From: Mykola Kvach
>
> If we call disable_nonboot_cpus on ARM64 with system_state set
> to SYS_STATE_suspend, the following assertion wi
Hi,
Mykola Kvach writes:
> From: Mykola Kvach
>
> System suspend may lead to a state where GIC would be powered down.
> Therefore, Xen should save/restore the context of GIC on suspend/resume.
>
> Note that the context consists of states of registers which are
> controlled by the hypervisor.
Hi Mykola,
Mykola Kvach writes:
> From: Mirela Simonovic
>
> System suspend may lead to a state where GIC would be powered down.
> Therefore, Xen should save/restore the context of GIC on suspend/resume.
>
> Note that the context consists of states of registers which are
> controlled by the hyp
Hi Mykola,
Mykola Kvach writes:
> From: Mykola Kvach
>
> This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPSCI
> (virtual PSCI) interface, allowing guests to request suspend via the PSCI
> v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).
>
> The implementation:
Leonid,
Leonid Komarianskyi writes:
> Hi Volodymyr,
>
> Thank you for you comment.
>
> On 21.08.25 18:46, Volodymyr Babchuk wrote:
>>
>> Leonid Komarianskyi writes:
>>
>>> Introduced two new helper functions for vGIC: vgic_is_valid_irq and
>>
Hi Leonid,
Leonid Komarianskyi writes:
> Hi Volodymyr,
>
> On 21.08.25 19:46, Volodymyr Babchuk wrote:
>>
>>
>>
>> Leonid Komarianskyi writes:
>>
>>> The Dom0 configuration logic in create_dom0() has been updated
>>> to acc
Julien Grall writes:
> On 21/08/2025 17:59, Volodymyr Babchuk wrote:
>> Julien Grall writes:
>>
>>> Hi,
>>>
>>> On 21/08/2025 16:59, Volodymyr Babchuk wrote:
>>>> Leonid Komarianskyi writes:
>>>>
>>>>> Current
Hi,
Leonid Komarianskyi writes:
> Introduced appropriate register definitions, helper macros,
> and initialization of required GICv3.1 distributor registers
> to support eSPI. This type of interrupt is handled in the
> same way as regular SPI interrupts, with the following
> differences:
>
> 1
Hi Leonid,
Leonid Komarianskyi writes:
> Introduced two new helper functions: gic_is_valid_irq and
> gic_is_shared_irq. The first function helps determine whether an IRQ
> number is less than the number of lines supported by hardware. The
> second function additionally checks if the IRQ number
Hi Leonid,
Leonid Komarianskyi writes:
> Implemented support for GICv3.1 extended SPI registers for vGICv3,
> allowing the emulation of eSPI-specific behavior for guest domains.
> The implementation includes read and write emulation for eSPI-related
> registers (e.g., GICD_ISENABLERnE, GICD_IR
Hi Julien,
Julien Grall writes:
> Hi,
>
> On 21/08/2025 16:59, Volodymyr Babchuk wrote:
>> Leonid Komarianskyi writes:
>>
>>> Currently, Xen does not support eSPI interrupts, leading
>>> to a data abort when such interrupts are defined in the DTS.
&
Leonid Komarianskyi writes:
> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
> requested by
Leonid Komarianskyi writes:
> The Dom0 configuration logic in create_dom0() has been updated
> to account for extended SPIs when supported by the hardware and
> enabled with CONFIG_GICV3_ESPI. These changes ensure the proper
> calculation of the maximum number of SPIs and eSPIs available for
Hi Leonid,
Leonid Komarianskyi writes:
> To properly deactivate guest interrupts and allow them to be retriggered
> after the initial trigger, the LR needs to be updated. The current
> implementation ignores interrupts outside the range specified by the mask
> 0x3FF, which only covers IRQ numbe
ctoring also simplifies the implementation of eSPI support in future
> changes.
>
> Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
>
> ---
> Changes in V2:
> - no changes
> ---
> xen/arch/arm/gic-v3.c | 99 ++
>
Leonid Komarianskyi writes:
> Currently, Xen does not support eSPI interrupts, leading
> to a data abort when such interrupts are defined in the DTS.
>
> This patch introduces a separate array to initialize up to
> 1024 interrupt descriptors in the eSPI range and adds the
> necessary defines and
Leonid Komarianskyi writes:
> Introduced two new helper functions for vGIC: vgic_is_valid_irq and
> vgic_is_shared_irq. The functions are similar to the newly introduced
> gic_is_valid_irq and gic_is_shared_irq, but they verify whether a vIRQ
> is available for a specific domain, while GIC-spec
provide fuzzer log and any crash input data as
artifacts. This crash data can be used later to replay the input to
reproduce the crash.
Signed-off-by: Volodymyr Babchuk
---
This patch is demonstration on how xen fuzzer can be integrated in
CI. With this setup, it can serve as smoke test, because 10
asically tells
fuzzer that test was completed successfully if Dom0 tries to shut
itself (or the whole machine) down.
Signed-off-by: Volodymyr Babchuk
---
Changes in v4:
- Fixed formatting in Kconfig.debug
- Removed spurious change
- Moved libfal-qemu.o in Makefile to the upper position to
:
- Added patch with experimental CI integration
- Severely reworked the main patch (see notes in the patch itself)
Volodymyr Babchuk (2):
xen: add libafl-qemu fuzzer support
ci: enable fuzzing for arm64
automation/gitlab-ci/build.yaml| 9 +++
automation/gitlab-ci/test.yaml | 33
rting from version 7 and LLVM/Clang starting from version 11
support -fprofile-update=atomic option, which forces coverage counter
updates to be atomic, which resolves the issue. As Xen runs mostly on
SMP systems, force use this option if it is supported by a compiler.
Signed-off-by: Volodym
GCC 15 (with commit "Add prime path coverage to gcc/gcov") added a
new, tenth counter. Reflect this in gcc_4_7.c.
Signed-off-by: Volodymyr Babchuk
---
xen/common/coverage/gcc_4_7.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/xen/common/coverage/gcc_4_7.c b/
rting from version 7 and LLVM/Clang starting from version 11
support -fprofile-update=atomic option, which forces coverage counter
updates to be atomic, which resolves the issue. As Xen runs mostly on
SMP systems, force use this option if it is supported by a compiler.
Signed-off-by: Volodymyr Babchuk
Hi Stefano,
Stefano Stabellini writes:
> On Wed, 7 May 2025, Volodymyr Babchuk wrote:
>> alpine-3.18-gcc-debug-arm64:
>> + extends: .gcc-arm64-build-debug
>> + variables:
>> +CONTAINER: alpine:3.18-arm64v8
>> +EXTRA_XEN_C
in the patch itself)
Volodymyr Babchuk (2):
xen: add libafl-qemu fuzzer support
ci: enable fuzzing for arm64
automation/gitlab-ci/build.yaml| 11
automation/gitlab-ci/test.yaml | 34 ++
docs/hypervisor-guide/fuzzing.rst | 91 ++
xen
asically tells
fuzzer that test was completed successfully if Dom0 tries to shut
itself (or the whole machine) down.
Signed-off-by: Volodymyr Babchuk
---
Changes in v3:
- Added fuzzer.h
- Kconfig entries were reworked to be more generic and support
other fuzzers in the future
- Moved all the c
provide fuzzer log and any crash input data as
artifacts. This crash data can be used later to replay the input to
reproduce the crash.
Signed-off-by: Volodymyr Babchuk
---
This patch is demonstration on how xen fuzzer can be integrated in
CI. With this setup, it can serve as smoke test, because 10
Hi John,
"L, John Preetham (893)" writes:
> Hi Volodymyr,
>
> Thank you once again for the detailed explanation and the helpful resources.
>
> With your guidance, I was able to bring up the XEN hypervisor on the R-Car
> H3e board successfully. I really appreciate your support.
>
I glad that
Jan Beulich writes:
> On 30.04.2025 04:17, Volodymyr Babchuk wrote:
>> Julien Grall writes:
>>>> --- /dev/null
>>>> +++ b/xen/arch/arm/include/asm/libafl_qemu_defs.h
>>>> @@ -0,0 +1,37 @@
>>>
>>> Missing license. Also, is this fil
Hi Julien,
Julien Grall writes:
[...]
>> diff --git a/xen/arch/arm/include/asm/libafl_qemu.h
>> b/xen/arch/arm/include/asm/libafl_qemu.h
>> new file mode 100644
>> index 00..b90cf48b9a
>> --- /dev/null
>> +++ b/xen/arch/arm/include/asm/libafl_qemu.h
>> @@ -0,0 +1,54 @@
>> +#ifndef LI
- opened a GCC bug
- make COV_FLAGS -> cov-flags-y convertion as part of the second patch
Changes in v3:
- Check if gcc accepts -fcondition-coverage
- Clarify why we use do { } loop
- Add Jan's R-b tag for PATCH 1/3
Changes in v2:
- Check for gcc 14, not gcc 14.1
- Reworked irq.c p
10 of LLVM profile data, where MC/DC support was added.
Also, use the opportunity to convert COV_FLAGS to cov-cflags-y, which
reduces amount of ifeqs in Rules.mk. Otherwise this patch had to add
another nesting level with "ifeq ($(CONFIG_CONDITION_COVERAGE),y)".
Signed-off-by: Vo
Hi Jan,
Jan Beulich writes:
> On 07.04.2025 18:46, Volodymyr Babchuk wrote:
>> --- a/xen/Rules.mk
>> +++ b/xen/Rules.mk
>> @@ -31,6 +31,7 @@ CFLAGS-y :=
>> AFLAGS-y :=
>> nocov-y :=
>> noubsan-y :=
>> +cov-flags-y :=
>
> Personally I wou
Stack protector is meant to be enabled on all architectures, but
currently it is tested (and enabled) only on ARM, so mention it in ARM
section.
Signed-off-by: Volodymyr Babchuk
Acked-by: Oleksii Kurochko
---
Changes in v7:
- Moved the change to v4.21
- Added Oleksii's acked-by tag
Ch
to enable stack protector" was
divided into two patches.
- Rebase onto Andrew's patch that removes -fno-stack-protector-all
- Tested on RISC-V thanks to Oleksii Kurochko
- Changes in individual patches covered in their respect commit
messages
Volodymyr Babchuk (3):
xen: com
, boot_stack_chk_guard_setup() should be
called prior to enabling secondary CPUs to avoid race with them.
Signed-off-by: Volodymyr Babchuk
Acked-by: Julien Grall
---
Changes in v6:
- Expanded the commit message
- Added Julien's A-b tag
Changes in v5:
- Call boot_stack_chk_guard_setup() from start_xen()
in
not called by Xen source code directly, and
only called by compiler-generated code, it does not needed to be
declared separately. So we need separate MISRA deviation for it.
Signed-off-by: Volodymyr Babchuk
---
Changes in v8:
- Code formatting fixes
- Added an explicit MISRA deviation for
convert COV_FLAGS to cov_flags-y, which
reduces amount of ifeqs in Rules.mk. Otherwise this patch had to add
another nesting level with "ifeq ($(CONFIG_CONDITION_COVERAGE),y)".
Signed-off-by: Volodymyr Babchuk
---
Changes in v4:
- Slight formatting fixes
- COV_FLAGS -> cov_flags-y
tive warning due to a
bug [1] in GCC.
Initialize "desc" with NULL to make GCC happy.
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119665
Signed-off-by: Volodymyr Babchuk
---
Changes in v4:
- Reverted back to initialing desc, per Jan's request
- Added link to the corre
Hi Anthony,
"Anthony PERARD" writes:
> On Sat, Apr 05, 2025 at 03:30:49AM +0000, Volodymyr Babchuk wrote:
>> --- a/xen/Rules.mk
>> +++ b/xen/Rules.mk
>> @@ -133,18 +133,19 @@ $(filter %.init.o,$(obj-y) $(obj-bin-y) $(extra-y)):
>> CFLAGS-y += -DIN
Hi Jan,
Jan Beulich writes:
> On 01.04.2025 03:17, Volodymyr Babchuk wrote:
>> --- a/xen/Kconfig
>> +++ b/xen/Kconfig
>> @@ -41,6 +41,11 @@ config CC_SPLIT_SECTIONS
>> config CC_HAS_UBSAN
>> def_bool $(cc-option,-fsanitize=undefined)
>>
>>
gcc 14 (with patch "Add condition coverage (MC/DC)") introduced 9th
gcov counter. Also this version can call new merge function
__gcov_merge_ior(), so we need a new stub for it.
Signed-off-by: Volodymyr Babchuk
Reviewed-by: Jan Beulich
---
Changes in v3:
- Added Jan's R-b tag
st we can have MC/DC with GCOV.
Changes in v3:
- Check if gcc accepts -fcondition-coverage
- Clarify why we use do { } loop
- Add Jan's R-b tag for PATCH 1/3
Changes in v2:
- Check for gcc 14, not gcc 14.1
- Reworked irq.c patch
Volodymyr Babchuk (3):
xen: gcov: add support for gcc 14
Condition coverage, also known as MC/DC (modified condition/decision
coverage) is a coverage metric that tracks separate outcomes in
boolean expressions.
This patch adds CONFIG_CONDITION_COVERAGE option to enable MC/DC for
GCC. Clang is not supported right now.
Signed-off-by: Volodymyr Babchuk
havior can be observed when building Xen with "-Og"
optimization level. Fix this by using "do { } while" loop instead of
"for" loop.
Signed-off-by: Volodymyr Babchuk
---
Changes in v3:
- Correct code style ("do {")
- Add comment describing why we need d
Condition coverage, also known as MC/DC (modified condition/decision
coverage) is a coverage metric that tracks separate outcomes in
boolean expressions.
This patch adds CONFIG_CONDITION_COVERAGE option to enable MC/DC for
GCC. Clang is not supported right now.
Signed-off-by: Volodymyr Babchuk
st we can have MC/DC with GCOV.
Changes in v2:
- Check for gcc 14, not gcc 14.1
- Reworked irq.c patch
Volodymyr Babchuk (3):
xen: gcov: add support for gcc 14
xen: x86: irq: use do-while loop in create_irq()
xen: debug: gcov: add condition coverage support
xen/Kconfig.debug
gcc 14 (with patch "Add condition coverage (MC/DC)") introduced 9th
gcov counter. Also this version can call new merge function
__gcov_merge_ior(), so we need a new stub for it.
Signed-off-by: Volodymyr Babchuk
---
Changes is v2:
- Check for gcc 14, not gcc 14.1
---
xen/commo
havior can be observed when building Xen with "-Og"
optimization level. Fix this by using "do { } while" loop instead of
"for" loop.
Signed-off-by: Volodymyr Babchuk
---
Changes in v2:
- Use do { } while loop instead of initializing desc with NULL
---
xen/arch/x
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