Hi Leonid,
On 05/09/2025 11:27, Leonid Komarianskyi wrote:
On 05.09.25 10:22, Julien Grall wrote:
Hi Leonid,
On 04/09/2025 21:01, Leonid Komarianskyi wrote:
+#ifdef CONFIG_GICV3_ESPI
+unsigned int gic_number_espis(void)
+{
+ return gic_hw_ops->info->nr_espi;
+}
+
+static void
So as soon as we re-enable the GIC we may receive interrupts we
can't handle. So I think we may need to initialize the eSPI part of the
distributor unconditionally. What do you think?
This could be handled as a follow-up but within the timeframe of Xen
4.21. So for this patch:
Acked-by
On 05/09/2025 11:05, Leonid Komarianskyi wrote:
On 05.09.25 10:10, Julien Grall wrote:
Hi Leonid,
On 04/09/2025 21:01, Leonid Komarianskyi wrote:
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/
asm/irq.h
index 5bc6475eb4..2ff2d07d6d 100644
--- a/xen/arch/arm/include/asm
security team when it comes to decide on whether we need to issue an XSA
(the more possibility, the more difficult it becomes).
There has been discussion on providing a small set of config (one could
be for certification purpose) that would be security supported. But I
don't think we come to a conclusion yet.
Cheers,
--
Julien Grall
est is not allowed to switch bitness. So I am not sure why we need
to hide EL1. Depending on the answer above, you might need to hide EL0
and have more code (TBC) to prevent 32-bit EL0 running.
Cheers,
--
Julien Grall
, or the domain
does not request such interrupts, the functionality remains unchanged.
Signed-off-by: Leonid Komarianskyi
Reviewed-by: Oleksandr Tyshchenko
This patch looks definitely better. Thanks for the rework!
Acked-by: Julien Grall
Cheers,
--
Julien Grall
maximum value of
992 interrupt lines, as it works currently.
Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
Reviewed-by: Oleksandr Tyshchenko
Acked-by: Julien Grall
Cheers,
--
Julien Grall
support them, or the CONFIG_GICV3_ESPI
option is disabled.
Signed-off-by: Leonid Komarianskyi
Reviewed-by: Oleksandr Tyshchenko
Acked-by: Julien Grall
Cheers,
--
Julien Grall
, which only covers IRQ numbers up to 1023. To enable
processing of eSPI interrupts, this patch updates the mask to 0x1FFF.
Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
Acked-by: Julien Grall
Cheers,
--
Julien Grall
Hi Leonid,
On 04/09/2025 21:01, Leonid Komarianskyi wrote:
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.h
index 5bc6475eb4..2ff2d07d6d 100644
--- a/xen/arch/arm/include/asm/irq.h
+++ b/xen/arch/arm/include/asm/irq.h
@@ -32,6 +32,10 @@ struct arch_irq_desc {
#defin
t I would actually prefer if there is no check
because I don't see the value.
+return false;
+#endif
+}
+
Cheers,
--
Julien Grall
ert (for the static inline
helper) or use BUILD_BUG_ON() to confirm that spi_base < espi_base
Cheers,
--
Julien Grall
Hi Leonid,
On 04/09/2025 14:09, Leonid Komarianskyi wrote:
On 04.09.25 15:27, Julien Grall wrote:
Hi Leonid,
On 03/09/2025 15:29, Leonid Komarianskyi wrote:
---
xen/arch/arm/Kconfig | 8 +
xen/arch/arm/include/asm/irq.h | 37
xen/arch/arm/irq.c
p;d->arch.vgic.ext_shared_irqs[i],
EXT_RANK_IDX2NUM(i), 0);
This would remove all the "if"s and the "EXT_RANK_IDX2NUM(rank->index)".
Cheers,
--
Julien Grall
.vgic.pending_irqs[irq - 32];
}
@@ -668,6 +858,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned int virq)
if ( !vgic_is_valid_line(d, virq) )
return false;
+if ( is_espi(virq) )
+return vgic_reserve_espi_virq(d, virq);
+
return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
}
@@ -685,7 +878,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
else
{
first = 32;
-end = vgic_num_irqs(d);
+end = vgic_num_alloc_irqs(d);
}
/*
Cheers,
--
Julien Grall
On 02/09/2025 18:15, Leonid Komarianskyi wrote:
Hi Julien,
Hi Leonid,
On 02.09.25 19:42, Julien Grall wrote:
Hi Leonid,
On 29/08/2025 17:06, Leonid Komarianskyi wrote:
The Dom0 and DomUs logic for the dom0less configuration in
create_dom0() and
arch_create_domUs() has been updated to
Hi Leonid,
On 02/09/2025 18:26, Leonid Komarianskyi wrote:
Hi Julien,
Thank you for your review and suggestions.
On 02.09.25 19:55, Julien Grall wrote:
Hi Leonid,
On 29/08/2025 17:06, Leonid Komarianskyi wrote:
@@ -782,46 +804,81 @@ static int
__vgic_v3_distr_common_mmio_write(const char
fs" everywhere (maybe using macros), I would rather
create a separate funciton to handle eSPIs.
Cheers,
--
Julien Grall
er_espis() > 0 )
+return ESPI_BASE_INTID + min(gic_number_espis(), 1024U) - 32;
+#endif
+
+return VGIC_DEF_NR_SPIS;
This is the only user of VGIC_DEF_NR_SPIS. Therefore, I would prefer if
we remove the define. This will avoid any confusion between the helper
and the define.
Cheers,
--
Julien Grall
Hi Oleksandr,
On 02/09/2025 15:00, Oleksandr Tyshchenko wrote:
On 02.09.25 15:19, Julien Grall wrote:
Hello Julien
On 02/09/2025 13:10, Orzel, Michal wrote:
On 02/09/2025 13:54, Julien Grall wrote:
Hi,
On 02/09/2025 11:18, Orzel, Michal wrote:
On 02/09/2025 11:49, Oleksandr
eSPI range.
Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
Acked-by: Julien Grall
Cheers,
--
Julien Grall
than
0x1fff. It is because eSPI range is 4096 - 5519. So in theory, it would
be ok to just add '0x1000'. But I think this is more confusion that it
is worth. So I would rather prefer if we use 0x1fff as this matches the
specification.
Cheers,
--
Julien Grall
e, it would be evaluated multiple time.
The alternative is to use a static inline helper which is usually preferred.
Cheers,
--
Julien Grall
On 02/09/2025 13:10, Orzel, Michal wrote:
On 02/09/2025 13:54, Julien Grall wrote:
Hi,
On 02/09/2025 11:18, Orzel, Michal wrote:
On 02/09/2025 11:49, Oleksandr Tyshchenko wrote:
The said sub-op is not supported on Arm, since it:
- does not support the buffered emulation (so
x27;t understand why we are trying to remove the subop...
Cheers,
--
Julien Grall
emulation (e.g. virtio
notification).
To be honest, I don't quite see the benefit of removing this code as
most of it is mainly generic.
Cheers,
--
Julien Grall
code
fairly optimized. An alternative would be to use #ifdef CONFIG_*. I
don't like it, but it could be a compromise if Oleksandr and Volodymyr
wants to push to remove #ifdef from CONFIG_IS_ESPI.
Cheers,
--
Julien Grall
f ( is_espi(irq) )
+return espi_to_desc(irq);
+
return &irq_desc[irq-NR_LOCAL_IRQS];
}
@@ -79,7 +133,7 @@ static int __init init_irq_data(void)
desc->action = NULL;
}
-return 0;
+return init_espi_data();
}
static int init_local_irq_data(unsigned int cpu)
Cheers,
--
Julien Grall
Hi Leonid,
On 28/08/2025 17:17, Leonid Komarianskyi wrote:
On 28.08.25 15:00, Julien Grall wrote:
Hi Leonid,
On 27/08/2025 19:24, Leonid Komarianskyi wrote:
Currently, many common functions perform the same operations to calculate
GIC register addresses. This patch consolidates the similar
disable_mpu_region_from_index(idx);
+context_sync_mpu();
+
+ out:
+spin_unlock(&xen_mpumap_lock);
+}
+
void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int flags)
{
-BUG_ON("unimplemented");
-return NULL;
+if ( !map_mm_range(start, start + len, flags) )
+return NULL;
+
+/* Mapped or already mapped */
+return maddr_to_virt(start);
}
/*
Cheers,
--
Julien Grall
This would also avoid the "tmp1" and "tmp2" which are not used by arm64.
Cheers,
--
Julien Grall
er or make it optional?
In fact, in the future we will want to initially have the directmap
optional on Arm with MMU, but ultimately will be removed.
Cheers,
--
Julien Grall
_page()?
Cheers,
--
Julien Grall
any
functional changes, as the helper functions follow the current vIRQ
index verification logic.
Signed-off-by: Leonid Komarianskyi
Acked-by: Julien Grall
Cheers,
--
Julien Grall
functions follow the current IRQ index verification logic.
Signed-off-by: Leonid Komarianskyi
Reviewed-by: Volodymyr Babchuk
With one remark below:
Acked-by: Julien Grall
---
Changes in V4:
- removed redundant parentheses
- added reviewed-by from Volodymyr Babchuk
Changes in V3:
- renamed
ach here */
+printk(XENLOG_WARNING "GICv3: WARNING: Invalid offset 0x%x for IRQ#%d",
NIT: I am not expecting the interrupt to be < 0. So it would be
preferable to use %u.
Acked-by: Julien Grall
Cheers,
--
Julien Grall
page_nr(page + i, nr_borrowers);
or yet more simply
fail:
while ( i-- )
put_page_nr(page + i, nr_borrowers);
See e.g. prepare_staticmem_pages() for a similar case.
+1 with Jan's comment.
Cheers,
--
Julien Grall
Hi Michal,
On 26/08/2025 12:44, Orzel, Michal wrote:
On 26/08/2025 12:48, Julien Grall wrote:
Hi,
On 26/08/2025 10:47, Dmytro Firsov wrote:
On 22.08.25 11:12, Orzel, Michal wrote:
On 06/08/2025 16:58, Dmytro Firsov wrote:
According to the Arm SMMUv3 spec (ARM IHI 0070), a system may have
res, which contains the required flag,
are not available in code parts that require cache maintenance).
Signed-off-by: Dmytro Firsov
With one remark below:
Reviewed-by: Julien Grall
diff --git a/xen/drivers/passthrough/arm/smmu-v3.h
b/xen/drivers/passthrough/arm/smmu-v3.h
index f090488
think a boolean per queue is the right appraoch.
Cheers,
--
Julien Grall
is is protected by is_64bit_domain().
So unless there is a strong reason to keep, I would rather prefer if we
remove the 64-bit.
Cheers,
--
Julien Grall
Grall
Cheers,
--
Julien Grall
EM_SUSPEND: Experimental
Experimental implies the feature is not complete. But it is unclear to
me what is missing (or I probably forgotten). Can this be clarified in
the commit message?
If there is nothing, then I think it can be a tech preview.
Cheers,
--
Julien Grall
e
"static" keyword.
For the latter, I think it would be better to provide a separate helper
that can be #ifdef.
[...]
Cheers,
--
Julien Grall
I don't have a particular
interest of using FrameBuffer on the raspberry PI. Feel free to revive
it and I would be happy to review them.
Cheers,
--
Julien Grall
e one in
get_addr_by_offset() should be sufficient.
Cheers,
--
Julien Grall
>= NR_LOCAL_IRQS && gic_is_valid_irq(irq));
Again, because of misleading name of gic_is_valid_irq() it may seem that
this function will return "true" for LPIs as well...
Even if we rename gic_is_valid_irq(), the function name would be
misleading because LPIs are shared. I think it would be better named
gic_is_spi(...);
Cheers,
--
Julien Grall
On 21/08/2025 17:59, Volodymyr Babchuk wrote:
Julien Grall writes:
Hi,
On 21/08/2025 16:59, Volodymyr Babchuk wrote:
Leonid Komarianskyi writes:
Currently, Xen does not support eSPI interrupts, leading
to a data abort when such interrupts are defined in the DTS.
This patch introduces
more gracefully in production.
Cheers,
--
Julien Grall
the Xen binary?
This is really confusing. Should it be something like espi_desc[NR_ESPI_IRQS]?
+1.
Cheers,
--
Julien Grall
functional change intended: on builds without ALTP2M the calls are
compiled out; on builds with ALTP2M behavior is unchanged.
Signed-off-by: Petr Beneš
Reviewed-by: Jan Beulich
Acked-by: Julien Grall # arm
Cheers,
--
Julien Grall
oot domain (currently, dom0) and
excluded from the allocation range.
Remove is_free_domid() helper as it is not needed now.
No functional change intended.
Signed-off-by: Denis Mukhin
Reviewed-by: Julien Grall
> Reviewed-by: Alejandro Vallejo
> ---> Changes since v15:
- fixup for che
ude a link to the successful GitLab pipeline run on your
+personal branch. This information can be added after the `---` line.
>> +For example:
+
+---
+Test CI pipeline:
+
https://gitlab.com/xen-project/people/your-username/xen/-/pipelines/1980129839
Cheers,
--
Julien Grall
Hi Andrew,
On 18/08/2025 09:18, Andrew Cooper wrote:
This was almost certainly copy&paste from x86. ARM does not us these nor
selects HAS_EX_TABLE, so drop the sections and their boundary markers.
No functional change.
Signed-off-by: Andrew Cooper
Acked-by: Julien Grall
Cheers,
--
are about performance. But it would be good to outline them as
I expect them to be pretty bad...
Cheers,
--
Julien Grall
Hi Jan,
On 12/08/2025 08:32, Jan Beulich wrote:
On 11.08.2025 23:21, Julien Grall wrote:
On 11/08/2025 21:30, Dmytro Prokopchuk1 wrote:
--- a/xen/common/grant_table.c
+++ b/xen/common/grant_table.c
@@ -330,9 +330,12 @@ shared_entry_header(struct grant_table *t, grant_ref_t ref
uot;dom0_mem" which has
correct memory size in both cases: regular dom0 boot and dom0less boot.
Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction")
Signed-off-by: Grygorii Strashko
Reviewed-by: Denis Mukhin
Reviewed-by: Jason Andryuk
Acked-by: Julien Grall
I have now committed the patch.
Cheers,
--
Julien Grall
On 11/08/2025 18:28, Julien Grall wrote:
Hi Mykola,
On 11/08/2025 09:45, Mykola Kvach wrote:
From: Mykola Kvach
If init_one_irq_desc() fails, init_local_irq_data() returns without
releasing local_irqs_type_lock, leading to a possible deadlock.
Release the lock before returning to ensure
.
Cheers,
--
Julien Grall
On 11/08/2025 18:32, Julien Grall wrote:
On 06/08/2025 14:58, Stewart Hildebrand wrote:
On 7/26/25 05:23, Julien Grall wrote:
Hi,
On 25/07/2025 15:01, Stewart Hildebrand wrote:
From: Stefano Stabellini
Up until f9f6b22abf1d "xen/arm: Map ITS doorbell register to IOMMU page
tables
Hi Jan,
On 12/08/2025 07:29, Jan Beulich wrote:
On 11.08.2025 19:24, Julien Grall wrote:
On 11/08/2025 14:01, Jan Beulich wrote:
Its uses in offline_page() and query_page_offline() make it reachable on
Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
code adde
Xen_Project_Patches
Patch diff itself looks good to me.
Cheers,
--
Julien Grall
you clarify what's the state of part 1? Is this already merged?
If not, then can you add a link in the cover letter? This would be
helpful to know the review ordering.
Cheers,
--
Julien Grall
Example::
default:
/* Notifier pattern */
break;
"
Cheers,
--
Julien Grall
Hi Stewart,
On 06/08/2025 14:58, Stewart Hildebrand wrote:
On 7/26/25 05:23, Julien Grall wrote:
Hi,
On 25/07/2025 15:01, Stewart Hildebrand wrote:
From: Stefano Stabellini
Up until f9f6b22abf1d "xen/arm: Map ITS doorbell register to IOMMU page
tables" the only caller of iommu_
t;xen/irq: Propagate the error from init_one_desc_irq() in
init_*_irq_data()")
Signed-off-by: Mykola Kvach
Reviewed-by: Denis Mukhin
Acked-by: Julien Grall
I will commit the patch soon.
Cheers,
--
Julien Grall
clear that the common use is for offlining.
The latter might be the simplest.
Cheers,
--
Julien Grall
Hi Roger,
On 11/08/2025 09:07, Roger Pau Monné wrote:
On Fri, Aug 08, 2025 at 06:21:29PM +0100, Julien Grall wrote:
Hi Roger,
On 05/08/2025 10:52, Roger Pau Monne wrote:
diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index a77b31071ed8..ba35bf1fe3bb 100644
--- a/xen/arch/arm
Hi Denis,
On 08/08/2025 03:20, dm...@proton.me wrote:
From: Denis Mukhin
Use %pd for domain identification in error/panic messages in create_dom0().
No functional change.
Signed-off-by: Denis Mukhin
Reviewed-by: Alejandro Vallejo
Acked-by: Jan Beulich
Acked-by: Julien Grall
Cheers
On 08/08/2025 18:56, Julien Grall wrote:
Hi Denis,
On 08/08/2025 03:20, dm...@proton.me wrote:
From: Denis Mukhin
Introduce some basic infrastructure for doing domain ID allocation
unit tests,
and add a few tests that ensure correctness of the domain ID allocator.
I am quite happy to
/lib/find-next-bit.c in test hardness code.
Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.
Signed-off-by: Denis Mukhin
With a couple of remarks below:
Acked-by: Julien Grall
---
Changes since v13:
- reworked bitops integration
- hooked xen/lib/find-next-bit.c
- cleaned up
oot domain (currently, dom0) and
excluded from the allocation range.
Remove is_free_domid() helper as it is not needed now.
No functional change intended.
Signed-off-by: Denis Mukhin
Reviewed-by: Julien Grall
Cheers,
--
Julien Grall
to reduce a bit the verbosity?
The rest of the logic looks fine. So:
Acked-by: Julien Grall # ARM
Cheers,
--
Julien Grall
: Julien Grall
---
Changes in v7:
- protect ffa_ctx list with a rw lock to allow several partinfo_get in
parallel but protect adding/removing entries.
Changes in v6:
- remove ACCESS_ONCE for guest_vers access and take the context lock
before modifying it
- move guest_vers in context declaration
a new PDX compression. Note all
PDX compression implementations are expected to provide a
pdx_is_region_compressible() that takes the same set of arguments.
Signed-off-by: Roger Pau Monné
Acked-by: Jan Beulich
Acked-by: Julien Grall
Cheers,
--
Julien Grall
: Jens Wiklander
Acked-by: Julien Grall
Cheers,
--
Julien Grall
Hi Bertrand,
On 17/07/2025 13:11, Bertrand Marquis wrote:
Add support for indirect messages between VMs.
This is only enabled if CONFIG_FFA_VM_TO_VM is selected.
Signed-off-by: Bertrand Marquis
Reviewed-by: Jens Wiklander
Acked-by: Julien Grall
Cheers,
--
Julien Grall
Hi Milan,
On Thu, 7 Aug 2025 at 17:55, Milan Djokic wrote:
> This patch series represents a rebase of an older patch series implemented
> and
> sumbitted by Rahul Singh as an RFC:
> https://patchwork.kernel.org/project/xen-devel/cover/cover.1669888522.git.rahul.si...@arm.com/
> .
> Original patc
Hi Grygorii,
On 06/08/2025 09:19, Grygorii Strashko wrote:
Hi Julien,
On 06.08.25 00:07, Julien Grall wrote:
Hi Grygorii,
On 05/08/2025 20:00, Grygorii Strashko wrote:
From: Grygorii Strashko
Call stack for dom0less hwdom case (1:1) memory:
create_domUs
|-construct_domU
; has
correct
memory size in both cases: regular dom0 boot and dom0less boot.
Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction")
Signed-off-by: Grygorii Strashko
Reviewed-by: Denis Mukhin
Reviewed-by: Jason Andryuk
Acked-by: Julien Grall
Cheers,
--
Julien Grall
i Strashko
Acked-by: Andrew Cooper
Reviewed-by: Denis Mukhin
Acked-by: Julien Grall
Cheers,
--
Julien Grall
. So it is better to
explicitly mention whether the kernel is 32-bit or 64-bit.
XEN_ARM_SUBARCH_ARMV7 = 1,
This name would not be correct. You can have a 32-bit Armv8 guest. A
better name is SUBARCH_AARCH32.
XEN_ARM_SUBARCH_AARCH64 = 2,
Cheers,
--
Julien Grall
it enabled).
#define ICH_LR_PHYSICAL_SHIFT32
#define ICH_LR_STATE_MASK0x3
#define ICH_LR_STATE_SHIFT 62
Cheers,
--
Julien Grall
? This would make easier to read the code.
Cheers,
--
Julien Grall
_IRQS || virq >= vgic_num_irqs(d)) && !is_espi(virq) )
... I don't quite understand why this (yet?) need a change. Can you clarify?
return -EINVAL;
desc = vgic_get_hw_irq_desc(d, NULL, virq);
Cheers,
--
Julien Grall
_desc *desc = irq_to_desc(irq);
+int rc = init_one_irq_desc(desc);
+
+if ( rc )
+return rc;
+
+desc->irq = irq;
+desc->action = NULL;
+}
+#endif
+
return 0;
}
Cheers,
--
Julien Grall
to deal with that logic. The rest (i.e.
ICFGR, IROUTER, IPRIORITY) should stay inlined.
Cheers,
--
Julien Grall
From: Julien Grall
When we can't split a superpage (on Arm p2m_split_superpage() returns false,
on x86 ept_split_superpage() returns 0), the caller is expected to clean
any PTE that may have been allocated. However, when we can't allocate
the page-tables 'entry' (arm) /
there is no mfn checking on the p2m_iommu_map_{rw,ro} p2m types during
unmap. Pass INVALID_MFN to guest_physmap_remove_page.
Signed-off-by: Stefano Stabellini
Signed-off-by: Stewart Hildebrand
Reviewed-by: Julien Grall
---
v4->v5:
* no change
v3->v4:
* no change
v2->v3:
* split ch
is_domain_direct_mapped(d) checks in arm_iommu_map_page and
arm_iommu_unmap_page into domain_use_host_layout(d) checks.
Drop stale in-code comment specific to grant table mappings.
Fixes: f9f6b22abf1d ("xen/arm: Map ITS doorbell register to IOMMU page tables")
Signed-off-by: Stefano Stabellini
Signed-off-by: Stewart Hildebrand
Reviewed-by: Julien Grall
Cheers,
--
Julien Grall
only used by one caller, I could see a benefit to be able to
use different value for the ratelimit. So I leaning towards keep the
code as-is.
Cheers,
--
Julien Grall
Hi,
On 23/07/2025 12:48, Grygorii Strashko wrote:
On 23.07.25 13:54, Orzel, Michal wrote:
On 23/07/2025 10:06, Julien Grall wrote:
On 23/07/2025 08:58, Grygorii Strashko wrote:
From: Grygorii Strashko
Hi,
Hi Grygorii,
Now Arm64 AArch32 guest support is always enabled and built-in
Hi,
On 23/07/2025 11:19, Grygorii Strashko wrote:
On 23.07.25 12:16, Julien Grall wrote:
On 23/07/2025 08:58, Grygorii Strashko wrote:
From: Grygorii Strashko
Move vcpu_switch_to_aarch64_mode() in arch_vcpu_create() callback
instead
of calling it manually from few different places after
said, I think there is still a problem
because with CDF_not_hypercall_target, you would not be able to have a
device-emulator for that domain. Is this intended?
Cheers,
Regards,
Jason
--
Julien Grall
striction of GICv3, the number of vCPUs in AFF0 is
Cheers,
--
Julien Grall
bit domain optional on Arm64. Then I think
it would be better to pass the domain type when the domain is created
(IOW add an extra flags to XEN_DOMCTL_createdomain). This will require
more work, but it will be a lot more robust.
Cheers,
--
Julien Grall
using CONFIG_* for
every single feature. This makes the testing a bit more complicated.
Can you clarify what the goal with this patch?
Cheers,
--
Julien Grall
if ( target && !is_hypercall_target(target) )
+return -EPERM;
if ( is_control_domain(src) )
return 0;
return -EPERM;
Cheers,
--
Julien Grall
On 16/07/2025 10:56, Julien Grall wrote:
On 15/07/2025 16:58, Stewart Hildebrand wrote:
On 7/14/25 18:47, Julien Grall wrote:
Hi Stewards,
On 14/07/2025 22:12, Stewart Hildebrand wrote:
On 7/12/25 06:08, Julien Grall wrote:
Hi Stefano,
On 11/07/2025 01:25, Stefano Stabellini wrote:
diff
Hi Stewart,
On 15/07/2025 16:58, Stewart Hildebrand wrote:
On 7/14/25 18:47, Julien Grall wrote:
Hi Stewards,
On 14/07/2025 22:12, Stewart Hildebrand wrote:
On 7/12/25 06:08, Julien Grall wrote:
Hi Stefano,
On 11/07/2025 01:25, Stefano Stabellini wrote:
diff --git a/xen/drivers
1 - 100 of 6221 matches
Mail list logo
