On 26.07.2022 16:43, Edwin Török wrote:
> --- a/xen/arch/x86/include/asm/msr-index.h
> +++ b/xen/arch/x86/include/asm/msr-index.h
> @@ -148,7 +148,7 @@
> #define MSR_INTERRUPT_SSP_TABLE 0x06a8
>
> #define MSR_X2APIC_FIRST0x0800
> -#define MSR_X2APIC_LAST
The latest Intel manual now says the X2APIC reserved range is only
0x800 to 0x8ff (NOT 0xbff). The AMD manual documents 0x800-0x8ff too.
There are non-X2APIC MSRs in the 0x900-0xbff range now:
e.g. 0x981 is IA32_TME_CAPABILITY, an architectural MSR.
The new MSR in this range appears to have been
