Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Jan Beulich
On 02.05.2023 15:02, Roger Pau Monné wrote: > On Tue, May 02, 2023 at 01:11:12PM +0200, Jan Beulich wrote: >> On 02.05.2023 13:05, Jan Beulich wrote: >>> On 02.05.2023 12:51, Roger Pau Monné wrote: On Tue, May 02, 2023 at 12:28:55PM +0200, Jan Beulich wrote: > On 02.05.2023 11:54, Andrew C

Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Roger Pau Monné
On Tue, May 02, 2023 at 01:11:12PM +0200, Jan Beulich wrote: > On 02.05.2023 13:05, Jan Beulich wrote: > > On 02.05.2023 12:51, Roger Pau Monné wrote: > >> On Tue, May 02, 2023 at 12:28:55PM +0200, Jan Beulich wrote: > >>> On 02.05.2023 11:54, Andrew Cooper wrote: > On 02/05/2023 10:22 am, Rog

Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Jan Beulich
On 02.05.2023 13:05, Jan Beulich wrote: > On 02.05.2023 12:51, Roger Pau Monné wrote: >> On Tue, May 02, 2023 at 12:28:55PM +0200, Jan Beulich wrote: >>> On 02.05.2023 11:54, Andrew Cooper wrote: On 02/05/2023 10:22 am, Roger Pau Monne wrote: > @@ -670,6 +674,11 @@ trampoline_setup: >

Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Jan Beulich
On 02.05.2023 12:51, Roger Pau Monné wrote: > On Tue, May 02, 2023 at 12:28:55PM +0200, Jan Beulich wrote: >> On 02.05.2023 11:54, Andrew Cooper wrote: >>> On 02/05/2023 10:22 am, Roger Pau Monne wrote: Ensure that the base address is 2M aligned, or else the page table entries created wou

Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Roger Pau Monné
On Tue, May 02, 2023 at 12:28:55PM +0200, Jan Beulich wrote: > On 02.05.2023 11:54, Andrew Cooper wrote: > > On 02/05/2023 10:22 am, Roger Pau Monne wrote: > >> Ensure that the base address is 2M aligned, or else the page table > >> entries created would be corrupt as reserved bits on the PDE end u

Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Andrew Cooper
On 02/05/2023 11:28 am, Roger Pau Monné wrote: > On Tue, May 02, 2023 at 10:54:55AM +0100, Andrew Cooper wrote: >> On 02/05/2023 10:22 am, Roger Pau Monne wrote: >>> Ensure that the base address is 2M aligned, or else the page table >>> entries created would be corrupt as reserved bits on the PDE e

Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Jan Beulich
On 02.05.2023 12:28, Roger Pau Monné wrote: > On Tue, May 02, 2023 at 10:54:55AM +0100, Andrew Cooper wrote: >> On 02/05/2023 10:22 am, Roger Pau Monne wrote: >>> Ensure that the base address is 2M aligned, or else the page table >>> entries created would be corrupt as reserved bits on the PDE end

Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Roger Pau Monné
On Tue, May 02, 2023 at 10:54:55AM +0100, Andrew Cooper wrote: > On 02/05/2023 10:22 am, Roger Pau Monne wrote: > > Ensure that the base address is 2M aligned, or else the page table > > entries created would be corrupt as reserved bits on the PDE end up > > set. > > > > We have found a broken firm

Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Jan Beulich
On 02.05.2023 11:54, Andrew Cooper wrote: > On 02/05/2023 10:22 am, Roger Pau Monne wrote: >> Ensure that the base address is 2M aligned, or else the page table >> entries created would be corrupt as reserved bits on the PDE end up >> set. >> >> We have found a broken firmware where the loader woul

Re: [PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Andrew Cooper
On 02/05/2023 10:22 am, Roger Pau Monne wrote: > Ensure that the base address is 2M aligned, or else the page table > entries created would be corrupt as reserved bits on the PDE end up > set. > > We have found a broken firmware where the loader would end up loading > Xen at a non 2M aligned region

[PATCH 1/2] x86/head: check base address alignment

2023-05-02 Thread Roger Pau Monne
Ensure that the base address is 2M aligned, or else the page table entries created would be corrupt as reserved bits on the PDE end up set. We have found a broken firmware where the loader would end up loading Xen at a non 2M aligned region, and that caused a very difficult to debug triple fault.