Re: [PATCH 3/5] x86/pv: Optimise prefetching in svm_load_segs()

2020-09-11 Thread Jan Beulich
On 10.09.2020 22:30, Andrew Cooper wrote: > On 10/09/2020 15:57, Jan Beulich wrote: >> On 09.09.2020 11:59, Andrew Cooper wrote: >>> Split into two functions. Passing a load of zeros in results in somewhat >>> poor >>> register scheduling in __context_switch(). >> I'm afraid I don't understand

Re: [PATCH 3/5] x86/pv: Optimise prefetching in svm_load_segs()

2020-09-10 Thread Andrew Cooper
On 10/09/2020 15:57, Jan Beulich wrote: > On 09.09.2020 11:59, Andrew Cooper wrote: >> Split into two functions. Passing a load of zeros in results in somewhat >> poor >> register scheduling in __context_switch(). > I'm afraid I don't understand why this would be, no matter that > I trust you

Re: [PATCH 3/5] x86/pv: Optimise prefetching in svm_load_segs()

2020-09-10 Thread Jan Beulich
On 09.09.2020 11:59, Andrew Cooper wrote: > Split into two functions. Passing a load of zeros in results in somewhat poor > register scheduling in __context_switch(). I'm afraid I don't understand why this would be, no matter that I trust you having observed this being the case: The registers

[PATCH 3/5] x86/pv: Optimise prefetching in svm_load_segs()

2020-09-09 Thread Andrew Cooper
Split into two functions. Passing a load of zeros in results in somewhat poor register scheduling in __context_switch(). Update the prefetching comment to note that the main point is the TLB fill. Reorder the writes in svm_load_segs() to access the VMCB fields in ascending order, which gets