On 18/09/2020 21:03, Jeff Kubascik wrote:
> On 9/17/2020 1:30 PM, Dario Faggioli wrote:
>> On Thu, 2020-09-17 at 15:59 +, Stewart Hildebrand wrote:
>>> On Thursday, September 17, 2020 11:20 AM, Dario Faggioli wrote:
On Thu, 2020-09-17 at 15:10 +, Stewart Hildebrand wrote:
>> It mig
On Fri, 2020-09-18 at 16:03 -0400, Jeff Kubascik wrote:
> On 9/17/2020 1:30 PM, Dario Faggioli wrote:
> > On Thu, 2020-09-17 at 15:59 +, Stewart Hildebrand wrote:
> > >
> > And don't think only to the need of writing the code (as you kind
> > of
> > have it already), but also to testing. As in
On 9/17/2020 1:30 PM, Dario Faggioli wrote:
>On Thu, 2020-09-17 at 15:59 +, Stewart Hildebrand wrote:
>> On Thursday, September 17, 2020 11:20 AM, Dario Faggioli wrote:
>>> On Thu, 2020-09-17 at 15:10 +, Stewart Hildebrand wrote:
> It might be worth to consider using just the core sched
On 9/17/2020 1:57 PM, Stewart Hildebrand wrote:
> On Thursday, September 17, 2020 12:19 PM, Andrew Cooper wrote:
>> On 17/09/2020 15:57, Stewart Hildebrand wrote:
>>> On Thursday, September 17, 2020 10:43 AM, Andrew Cooper wrote:
On 16/09/2020 19:18, Jeff Kubascik wrote:
> +/*
> + * A
On 17/09/2020 15:57, Stewart Hildebrand wrote:
> On Thursday, September 17, 2020 10:43 AM, Andrew Cooper wrote:
>> On 16/09/2020 19:18, Jeff Kubascik wrote:
>>> +/*
>>> + * A handle with all zeros represents domain 0 if present, otherwise idle
>>> UNIT
>>> + */
>>> +#define DOM0_HANDLE ((const xen
On 16/09/2020 19:18, Jeff Kubascik wrote:
> +/*
> + * A handle with all zeros represents domain 0 if present, otherwise idle
> UNIT
> + */
> +#define DOM0_HANDLE ((const xen_domain_handle_t){0})
This isn't accurate.
There are systems where dom0 doesn't have a zero UUID (XenServer for
one), and i
On Thursday, September 17, 2020 12:19 PM, Andrew Cooper wrote:
>On 17/09/2020 15:57, Stewart Hildebrand wrote:
>> On Thursday, September 17, 2020 10:43 AM, Andrew Cooper wrote:
>>> On 16/09/2020 19:18, Jeff Kubascik wrote:
+/*
+ * A handle with all zeros represents domain 0 if present, ot
On Thu, 2020-09-17 at 15:59 +, Stewart Hildebrand wrote:
> On Thursday, September 17, 2020 11:20 AM, Dario Faggioli wrote:
> > On Thu, 2020-09-17 at 15:10 +, Stewart Hildebrand wrote:
> > > > It might be worth to consider using just the core scheduling
> > > > framework
> > > > in order to
On Thursday, September 17, 2020 11:20 AM, Dario Faggioli wrote:
>On Thu, 2020-09-17 at 15:10 +, Stewart Hildebrand wrote:
>> On Thursday, September 17, 2020 5:04 AM, Jürgen Groß wrote:
>> > On 16.09.20 20:18, Jeff Kubascik wrote:
>> > > This change is an overhaul of the ARINC653 scheduler to en
On Thu, 2020-09-17 at 15:10 +, Stewart Hildebrand wrote:
> On Thursday, September 17, 2020 5:04 AM, Jürgen Groß wrote:
> > On 16.09.20 20:18, Jeff Kubascik wrote:
> > > This change is an overhaul of the ARINC653 scheduler to enable
> > > CAST-32A
> > > multicore scheduling. CAST-32A specifies t
On 17.09.20 17:10, Stewart Hildebrand wrote:
On Thursday, September 17, 2020 5:04 AM, Jürgen Groß wrote:
On 16.09.20 20:18, Jeff Kubascik wrote:
This change is an overhaul of the ARINC653 scheduler to enable CAST-32A
multicore scheduling. CAST-32A specifies that only one partition
(domain) can
On Thursday, September 17, 2020 5:04 AM, Jürgen Groß wrote:
>On 16.09.20 20:18, Jeff Kubascik wrote:
>> This change is an overhaul of the ARINC653 scheduler to enable CAST-32A
>> multicore scheduling. CAST-32A specifies that only one partition
>> (domain) can run during a minor frame, but that doma
On Thursday, September 17, 2020 10:43 AM, Andrew Cooper wrote:
>On 16/09/2020 19:18, Jeff Kubascik wrote:
>> +/*
>> + * A handle with all zeros represents domain 0 if present, otherwise idle
>> UNIT
>> + */
>> +#define DOM0_HANDLE ((const xen_domain_handle_t){0})
>
>This isn't accurate.
>
>There a
On 16.09.20 20:18, Jeff Kubascik wrote:
This change is an overhaul of the ARINC653 scheduler to enable CAST-32A
multicore scheduling. CAST-32A specifies that only one partition
(domain) can run during a minor frame, but that domain is now allowed to
have more than one vCPU.
It might be worth to
This change is an overhaul of the ARINC653 scheduler to enable CAST-32A
multicore scheduling. CAST-32A specifies that only one partition
(domain) can run during a minor frame, but that domain is now allowed to
have more than one vCPU.
Changes include:
- Each pCPU now has its own private structure.
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