Re: [PATCH v4 3/4] x86: limit issuing of IBPB during context switch

2023-12-18 Thread Jan Beulich
On 18.12.2023 16:19, Roger Pau Monné wrote: > On Tue, Feb 14, 2023 at 05:11:40PM +0100, Jan Beulich wrote: >> --- a/xen/arch/x86/domain.c >> +++ b/xen/arch/x86/domain.c >> @@ -2005,17 +2005,26 @@ void context_switch(struct vcpu *prev, s >> } >> else >> { >> +unsigned int feat

Re: [PATCH v4 3/4] x86: limit issuing of IBPB during context switch

2023-12-18 Thread Jan Beulich
On 18.12.2023 16:19, Roger Pau Monné wrote: > On Tue, Feb 14, 2023 at 05:11:40PM +0100, Jan Beulich wrote: >> When the outgoing vCPU had IBPB issued and RSB overwritten upon entering >> Xen, then there's no need for a 2nd barrier during context switch. >> >> Note that SCF_entry_ibpb is always clear

Re: [PATCH v4 3/4] x86: limit issuing of IBPB during context switch

2023-12-18 Thread Roger Pau Monné
On Tue, Feb 14, 2023 at 05:11:40PM +0100, Jan Beulich wrote: > When the outgoing vCPU had IBPB issued and RSB overwritten upon entering > Xen, then there's no need for a 2nd barrier during context switch. > > Note that SCF_entry_ibpb is always clear for the idle domain, so no > explicit idle domai

[PATCH v4 3/4] x86: limit issuing of IBPB during context switch

2023-02-14 Thread Jan Beulich
When the outgoing vCPU had IBPB issued and RSB overwritten upon entering Xen, then there's no need for a 2nd barrier during context switch. Note that SCF_entry_ibpb is always clear for the idle domain, so no explicit idle domain check is needed to augment the feature check (which is simply inappli