[PATCH v6 3/4] xen/vpci: header: status register handler

2023-09-08 Thread Stewart Hildebrand
Introduce a handler for the PCI status register, with ability to mask the capabilities bit. The status register contains RsvdZ bits, read-only bits, and write-1-to-clear bits, so introduce bitmasks to handle these in vPCI. If a bit in the bitmask is set, then the special meaning applies: rsvdz_m

Re: [PATCH v6 3/4] xen/vpci: header: status register handler

2023-09-11 Thread Jan Beulich
On 09.09.2023 04:16, Stewart Hildebrand wrote: > @@ -544,6 +545,18 @@ static int cf_check init_bars(struct pci_dev *pdev) > if ( rc ) > return rc; > > +/* > + * If mask_cap_list is true, PCI_STATUS_CAP_LIST will be set in both > + * rsvdz_mask and ro_mask, and thus will

Re: [PATCH v6 3/4] xen/vpci: header: status register handler

2023-09-11 Thread Stewart Hildebrand
On 9/11/23 07:10, Jan Beulich wrote: > On 09.09.2023 04:16, Stewart Hildebrand wrote: >> @@ -544,6 +545,18 @@ static int cf_check init_bars(struct pci_dev *pdev) >> if ( rc ) >> return rc; >> >> +/* >> + * If mask_cap_list is true, PCI_STATUS_CAP_LIST will be set in both >> +