Hi Ayan,
On 04/05/2023 09:57, Ayan Kumar Halder wrote:
On 03/05/2023 18:43, Julien Grall wrote:
Hi Ayan,
Hi Julien,
On 03/05/2023 17:49, Ayan Kumar Halder wrote:
On 03/05/2023 08:40, Julien Grall wrote:
Hi,
Hi Julien,
Title: Did you mean "Enable spin table"?
Yes, that would be more c
On 03/05/2023 18:43, Julien Grall wrote:
Hi Ayan,
Hi Julien,
On 03/05/2023 17:49, Ayan Kumar Halder wrote:
On 03/05/2023 08:40, Julien Grall wrote:
Hi,
Hi Julien,
Title: Did you mean "Enable spin table"?
Yes, that would be more concrete.
On 02/05/2023 11:58, Ayan Kumar Halder wrote:
On Wed, 3 May 2023, Julien Grall wrote:
> Hi Stefano,
>
> On 03/05/2023 18:54, Stefano Stabellini wrote:
> > On Wed, 3 May 2023, Julien Grall wrote:
> > > Hi Stefano,
> > >
> > > On 03/05/2023 00:55, Stefano Stabellini wrote:
> > > > > +{
> > > > > +printk("CPU%d: No release addr\n",
Hi Stefano,
On 03/05/2023 18:54, Stefano Stabellini wrote:
On Wed, 3 May 2023, Julien Grall wrote:
Hi Stefano,
On 03/05/2023 00:55, Stefano Stabellini wrote:
+{
+printk("CPU%d: No release addr\n", cpu);
+return -ENODEV;
+}
+
+release = ioremap_nocache(cpu_release_a
On Wed, 3 May 2023, Julien Grall wrote:
> Hi Stefano,
>
> On 03/05/2023 00:55, Stefano Stabellini wrote:
> > > +{
> > > +printk("CPU%d: No release addr\n", cpu);
> > > +return -ENODEV;
> > > +}
> > > +
> > > +release = ioremap_nocache(cpu_release_addr[cpu], 4);
> > > +
Hi Ayan,
On 03/05/2023 17:49, Ayan Kumar Halder wrote:
On 03/05/2023 08:40, Julien Grall wrote:
Hi,
Hi Julien,
Title: Did you mean "Enable spin table"?
Yes, that would be more concrete.
On 02/05/2023 11:58, Ayan Kumar Halder wrote:
On some of the Arm32 based systems (eg Cortex-R52), smpb
On 03/05/2023 08:40, Julien Grall wrote:
Hi,
Hi Julien,
Title: Did you mean "Enable spin table"?
Yes, that would be more concrete.
On 02/05/2023 11:58, Ayan Kumar Halder wrote:
On some of the Arm32 based systems (eg Cortex-R52), smpboot is
supported.
Same here.
Yes
In these systems
Hi Stefano,
On 03/05/2023 00:55, Stefano Stabellini wrote:
+{
+printk("CPU%d: No release addr\n", cpu);
+return -ENODEV;
+}
+
+release = ioremap_nocache(cpu_release_addr[cpu], 4);
+if ( !release )
+{
+dprintk(XENLOG_ERR, "CPU%d: Unable to map release a
Hi,
Title: Did you mean "Enable spin table"?
On 02/05/2023 11:58, Ayan Kumar Halder wrote:
On some of the Arm32 based systems (eg Cortex-R52), smpboot is supported.
Same here.
In these systems PSCI may not always be supported. In case of Cortex-R52, there
is no EL3 or secure mode. Thus, PSC
On Tue, 2 May 2023, Ayan Kumar Halder wrote:
> On some of the Arm32 based systems (eg Cortex-R52), smpboot is supported.
> In these systems PSCI may not always be supported. In case of Cortex-R52,
> there
> is no EL3 or secure mode. Thus, PSCI is not supported as it requires EL3.
>
> Thus, we use
On some of the Arm32 based systems (eg Cortex-R52), smpboot is supported.
In these systems PSCI may not always be supported. In case of Cortex-R52, there
is no EL3 or secure mode. Thus, PSCI is not supported as it requires EL3.
Thus, we use 'spin-table' mechanism to boot the secondary cpus. The pr
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