Re: [RFC PATCH v1 07/12] Arm: GICv3: Emulate ICH_LR_EL2 on AArch32

2022-10-28 Thread Julien Grall
On 28/10/2022 15:22, Ayan Kumar Halder wrote: On 22/10/2022 12:03, Julien Grall wrote: Hi Ayan, Hi Julien, I need a clarification. Title: Xen doesn't emulate ICH_LR* (we don't expose them to the guest). Instead Xen will use the registers and your patch provides wrappers to use

Re: [RFC PATCH v1 07/12] Arm: GICv3: Emulate ICH_LR_EL2 on AArch32

2022-10-28 Thread Ayan Kumar Halder
On 22/10/2022 12:03, Julien Grall wrote: Hi Ayan, Hi Julien, I need a clarification. Title: Xen doesn't emulate ICH_LR* (we don't expose them to the guest). Instead Xen will use the registers and your patch provides wrappers to use access the registers on 32-bit host. On 21/10/2022

Re: [RFC PATCH v1 07/12] Arm: GICv3: Emulate ICH_LR_EL2 on AArch32

2022-10-22 Thread Julien Grall
Hi Ayan, Title: Xen doesn't emulate ICH_LR* (we don't expose them to the guest). Instead Xen will use the registers and your patch provides wrappers to use access the registers on 32-bit host. On 21/10/2022 16:31, Ayan Kumar Halder wrote: diff --git

[RFC PATCH v1 07/12] Arm: GICv3: Emulate ICH_LR_EL2 on AArch32

2022-10-21 Thread Ayan Kumar Halder
Refer "Arm IHI 0069H ID020922", 12.4.6, Interrupt Controller List Registers AArch64 System register ICH_LR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ICH_LR[31:0]. AArch64 System register ICH_LR_EL2 bits [63:32] are architecturally mapped to AArch32 System register