> -Original Message-
> From: Julien Grall [mailto:julien.gr...@arm.com]
> Sent: 2019年1月30日 21:49
> To: Peng Fan ; sstabell...@kernel.org
> Cc: xen-devel@lists.xenproject.org; Andre Przywara
>
> Subject: Re: [PATCH] arm: gic-v3: clear GICR active interrupts
>
> Hi,
>
> On 30/01/2019 13:
Hi,
On 30/01/2019 13:36, Peng Fan wrote:
Each ICACTIVER0 registers hold the active bit for 32 interrupts.
However, this code assumes the register only hold 4 interrupts. So
this will write to unwanted area.
There are only 16 SGIs, so it fits in one write to ICACTIVER0. As
wrote above, you also
> -Original Message-
> From: Xen-devel [mailto:xen-devel-boun...@lists.xenproject.org] On Behalf
> Of Peng Fan
> Sent: 2019年1月30日 21:24
> To: Julien Grall ; sstabell...@kernel.org
> Cc: xen-devel@lists.xenproject.org; Andre Przywara
>
> Subject: Re: [Xen-de
Hi Julien
> -Original Message-
> From: Julien Grall [mailto:julien.gr...@arm.com]
> Sent: 2019年1月30日 20:06
> To: Peng Fan ; sstabell...@kernel.org
> Cc: xen-devel@lists.xenproject.org; Andre Przywara
>
> Subject: Re: [PATCH] arm: gic-v3: clear GICR active interrupts
>
> Hi
>
> Replying
Hi
Replying to this thread again.
On 22/01/2019 10:54, Julien Grall wrote:
Hi Peng,
The commit title is a bit confusing. It suggests that all interrupts should be
deactivated at boot, however you are only deactivating the SGIs.
On 1/22/19 2:35 AM, Peng Fan wrote:
On i.MX8, we implemented p
On 24/01/2019 07:22, Peng Fan wrote:
Hi Julien
Hi Peng,
Are you ok with the following patch?
This looks ok. Please resend it formally with the tag for-4.12 and the release
manager (jgr...@suse.com) in CC.
arm: gic: deactivate sgi immediately after eoi
On i.MX8, we implemente
Hi Julien
> -Original Message-
> From: Julien Grall [mailto:julien.gr...@arm.com]
> Sent: 2019年1月22日 18:55
> To: Peng Fan ; sstabell...@kernel.org
> Cc: xen-devel@lists.xenproject.org; Andre Przywara
>
> Subject: Re: [PATCH] arm: gic-v3: clear GICR active interrupts
>
> Hi Peng,
>
> The
Hi Peng,
The commit title is a bit confusing. It suggests that all interrupts
should be deactivated at boot, however you are only deactivating the SGIs.
On 1/22/19 2:35 AM, Peng Fan wrote:
On i.MX8, we implemented partition reboot which means Cortex-A reboot
will not impact M4 cores and Syste
On i.MX8, we implemented partition reboot which means Cortex-A reboot
will not impact M4 cores and System control Unit core. However GICv3
is not reset because hardware design.
The gic-v3 controller is configured with EOImode to 1, so during xen
reboot, GIC_SGI_CALL_FUNCTION interrupt from CPU0 to
