> -Original Message-
> From: Andrew Cooper
> Sent: 17 October 2018 14:24
> To: Paul Durrant ; xen-devel@lists.xenproject.org
> Cc: George Dunlap ; Jan Beulich
> ; Wei Liu
> Subject: Re: [PATCH] x86/mm/p2m: don't needlessly limit MMIO mapping order
> to 4k
>
> On 16/10/18 15:41, Paul
On 16/10/18 15:41, Paul Durrant wrote:
> The P2M common code currently restricts the MMIO mapping order of any
> domain with IOMMU mappings, but that is not using shared tables, to 4k.
> This has been shown to have a huge performance cost when passing through
> a PCI device with a very large BAR
> -Original Message-
> From: Roger Pau Monne
> Sent: 16 October 2018 17:27
> To: Paul Durrant
> Cc: xen-devel@lists.xenproject.org; George Dunlap
> ; Andrew Cooper ; Wei
> Liu ; Jan Beulich
> Subject: Re: [Xen-devel] [PATCH] x86/mm/p2m: don't needlessly limit MM
On Tue, Oct 16, 2018 at 03:41:55PM +0100, Paul Durrant wrote:
> The P2M common code currently restricts the MMIO mapping order of any
> domain with IOMMU mappings, but that is not using shared tables, to 4k.
> This has been shown to have a huge performance cost when passing through
> a PCI device
On 10/16/2018 03:41 PM, Paul Durrant wrote:
> The P2M common code currently restricts the MMIO mapping order of any
> domain with IOMMU mappings, but that is not using shared tables, to 4k.
> This has been shown to have a huge performance cost when passing through
> a PCI device with a very large
The P2M common code currently restricts the MMIO mapping order of any
domain with IOMMU mappings, but that is not using shared tables, to 4k.
This has been shown to have a huge performance cost when passing through
a PCI device with a very large BAR (e.g. NVIDIA P40), increasing the guest
boot
