On 02/03/2018 18:33, Stefano Stabellini wrote:
On Fri, 2 Mar 2018, Stefano Stabellini wrote:
On Fri, 2 Mar 2018, Julien Grall wrote:
Hi,
On 01/03/18 23:27, Stefano Stabellini wrote:
See the corresponding Linux commit as reference:
commit f91e2c3bd427239c198351f44814dd39db91afe0
Aut
On Fri, 2 Mar 2018, Stefano Stabellini wrote:
> On Fri, 2 Mar 2018, Julien Grall wrote:
> > Hi,
> >
> > On 01/03/18 23:27, Stefano Stabellini wrote:
> > > See the corresponding Linux commit as reference:
> > >
> > >commit f91e2c3bd427239c198351f44814dd39db91afe0
> > >Author: Catalin Marin
Thanks, I'll mention it in the commit message.
On Fri, 2 Mar 2018, Julien Grall wrote:
> Hi,
>
> I forgot to mention in the title:
>
> You read the minimum D-Cache line size. The minimum I-Cache line size is read
> from CTR_EL0.IminLine.
>
> Cheers,
>
> On 01/03/18 23:27, Stefano Stabellini wr
On Fri, 2 Mar 2018, Julien Grall wrote:
> Hi,
>
> On 01/03/18 23:27, Stefano Stabellini wrote:
> > See the corresponding Linux commit as reference:
> >
> >commit f91e2c3bd427239c198351f44814dd39db91afe0
> >Author: Catalin Marinas
> >Date: Tue Dec 7 16:52:04 2010 +0100
> >
> >
Hi,
I forgot to mention in the title:
You read the minimum D-Cache line size. The minimum I-Cache line size is
read from CTR_EL0.IminLine.
Cheers,
On 01/03/18 23:27, Stefano Stabellini wrote:
See the corresponding Linux commit as reference:
commit f91e2c3bd427239c198351f44814dd39db91afe
Hi,
On 01/03/18 23:27, Stefano Stabellini wrote:
See the corresponding Linux commit as reference:
commit f91e2c3bd427239c198351f44814dd39db91afe0
Author: Catalin Marinas
Date: Tue Dec 7 16:52:04 2010 +0100
ARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on A
See the corresponding Linux commit as reference:
commit f91e2c3bd427239c198351f44814dd39db91afe0
Author: Catalin Marinas
Date: Tue Dec 7 16:52:04 2010 +0100
ARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on ARMv7
The current implementation of the dcache_lin
