On 29.01.2020 14:08, Andrew Cooper wrote:
> On 29/01/2020 08:17, Jan Beulich wrote:
>> On 28.01.2020 18:14, Andrew Cooper wrote:
>>> On 28/01/2020 13:59, Jan Beulich wrote:
On 27.01.2020 21:21, Andrew Cooper wrote:
> Without this fix, there is apparently a problem with Roger's "[PATCH v3
On 29/01/2020 08:17, Jan Beulich wrote:
> On 28.01.2020 18:14, Andrew Cooper wrote:
>> On 28/01/2020 13:59, Jan Beulich wrote:
>>> On 27.01.2020 21:21, Andrew Cooper wrote:
Without this fix, there is apparently a problem with Roger's "[PATCH v3
7/7]
x86/tlb: use Xen L0 assisted TLB
On 28.01.2020 18:14, Andrew Cooper wrote:
> On 28/01/2020 13:59, Jan Beulich wrote:
>> On 27.01.2020 21:21, Andrew Cooper wrote:
>>> Without this fix, there is apparently a problem with Roger's "[PATCH v3 7/7]
>>> x86/tlb: use Xen L0 assisted TLB flush when available" on native AMD
>>> hardware.
>
On 28/01/2020 13:59, Jan Beulich wrote:
> On 27.01.2020 21:21, Andrew Cooper wrote:
>> Currently when booting native on AMD hardware, cpuidmask_defaults._1cd gets
>> configured with the HYPERVISOR bit before native CPUID is scanned for feature
>> bits.
>>
>> This results in cpu_has_hypervisor becom
On 27.01.2020 21:21, Andrew Cooper wrote:
> Currently when booting native on AMD hardware, cpuidmask_defaults._1cd gets
> configured with the HYPERVISOR bit before native CPUID is scanned for feature
> bits.
>
> This results in cpu_has_hypervisor becoming set as part of identify_cpu(), and
> ends
On 28/01/2020 11:58, Roger Pau Monné wrote:
> On Tue, Jan 28, 2020 at 11:21:14AM +, Andrew Cooper wrote:
>> On 28/01/2020 10:39, Roger Pau Monné wrote:
This is one of two possible approaches, and both have their downsides.
This
one takes an extra hit on context switches between
On Tue, Jan 28, 2020 at 11:21:14AM +, Andrew Cooper wrote:
> On 28/01/2020 10:39, Roger Pau Monné wrote:
> >
> >> This is one of two possible approaches, and both have their downsides.
> >> This
> >> one takes an extra hit on context switches between PV vcpus and idle/hvm,
> >> as
> >> they
On 28/01/2020 10:39, Roger Pau Monné wrote:
>
>> This is one of two possible approaches, and both have their downsides. This
>> one takes an extra hit on context switches between PV vcpus and idle/hvm, as
>> they will usually differ in HYPERVISOR bit.
>>
>> The other approach is to order things mo
On Mon, Jan 27, 2020 at 08:21:21PM +, Andrew Cooper wrote:
> Currently when booting native on AMD hardware, cpuidmask_defaults._1cd gets
> configured with the HYPERVISOR bit before native CPUID is scanned for feature
> bits.
>
> This results in cpu_has_hypervisor becoming set as part of identi
Currently when booting native on AMD hardware, cpuidmask_defaults._1cd gets
configured with the HYPERVISOR bit before native CPUID is scanned for feature
bits.
This results in cpu_has_hypervisor becoming set as part of identify_cpu(), and
ends up appearing in the raw and host CPU policies. Nothin
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