Re: [Xen-devel] [PATCH SpectreV1+L1TF v4 09/11] x86/vioapic: block speculative out-of-bound accesses

2019-01-28 Thread Norbert Manthey
On 1/28/19 12:12, Jan Beulich wrote: On 28.01.19 at 12:03, wrote: >> On 1/25/19 17:34, Jan Beulich wrote: >> On 23.01.19 at 12:57, wrote: @@ -212,7 +217,12 @@ static void vioapic_write_redirent( struct hvm_irq *hvm_irq = hvm_domain_irq(d); union vioapic_redir_ent

Re: [Xen-devel] [PATCH SpectreV1+L1TF v4 09/11] x86/vioapic: block speculative out-of-bound accesses

2019-01-28 Thread Jan Beulich
>>> On 28.01.19 at 12:03, wrote: > On 1/25/19 17:34, Jan Beulich wrote: > On 23.01.19 at 12:57, wrote: >>> @@ -212,7 +217,12 @@ static void vioapic_write_redirent( >>> struct hvm_irq *hvm_irq = hvm_domain_irq(d); >>> union vioapic_redir_entry *pent, ent; >>> int unmasked = 0; >

Re: [Xen-devel] [PATCH SpectreV1+L1TF v4 09/11] x86/vioapic: block speculative out-of-bound accesses

2019-01-28 Thread Norbert Manthey
On 1/25/19 17:34, Jan Beulich wrote: On 23.01.19 at 12:57, wrote: >> @@ -66,6 +67,9 @@ static struct hvm_vioapic *gsi_vioapic(const struct domain >> *d, >> { >> unsigned int i; >> >> +/* Make sure the compiler does not optimize the initialization */ >> +OPTIMIZER_HIDE_VAR(pin

Re: [Xen-devel] [PATCH SpectreV1+L1TF v4 09/11] x86/vioapic: block speculative out-of-bound accesses

2019-01-25 Thread Jan Beulich
>>> On 23.01.19 at 12:57, wrote: > @@ -66,6 +67,9 @@ static struct hvm_vioapic *gsi_vioapic(const struct domain > *d, > { > unsigned int i; > > +/* Make sure the compiler does not optimize the initialization */ > +OPTIMIZER_HIDE_VAR(pin); Since there's no initialization here, I t

[Xen-devel] [PATCH SpectreV1+L1TF v4 09/11] x86/vioapic: block speculative out-of-bound accesses

2019-01-23 Thread Norbert Manthey
When interacting with io apic, a guest can specify values that are used as index to structures, and whose values are not compared against upper bounds to prevent speculative out-of-bound accesses. This change prevents these speculative accesses. This commit is part of the SpectreV1+L1TF mitigation