Re: [Xen-devel] [PATCH v2] xen/arm: Handle unimplemented VGICv3 dist registers as RAZ/WI

Hey Julien, On 2/1/2020 6:45 AM, Julien Grall wrote: > Hi, > > On 31/01/2020 20:10, Jeff Kubascik wrote: >> Per the ARM Generic Interrupt Controller Architecture Specification (ARM >> IHI 0069E), reserved registers should generally be treated as RAZ/WI. >> To simplify the VGICv3 design and

Re: [Xen-devel] [PATCH v2] xen/arm: Handle unimplemented VGICv3 dist registers as RAZ/WI

Hi, On 31/01/2020 20:10, Jeff Kubascik wrote: Per the ARM Generic Interrupt Controller Architecture Specification (ARM IHI 0069E), reserved registers should generally be treated as RAZ/WI. To simplify the VGICv3 design and improve guest compatability, treat the Typo: compatibility default

[Xen-devel] [PATCH v2] xen/arm: Handle unimplemented VGICv3 dist registers as RAZ/WI

Per the ARM Generic Interrupt Controller Architecture Specification (ARM IHI 0069E), reserved registers should generally be treated as RAZ/WI. To simplify the VGICv3 design and improve guest compatability, treat the default case for GICD registers as read_as_zero/write_ignore. Signed-off-by: Jeff