Re: [Xen-devel] [PATCH v5 2/4] x86/HVM: implement memory read caching for insn emulation

2020-03-10 Thread Jan Beulich
On 10.03.2020 03:39, Tian, Kevin wrote: >> From: Jan Beulich >> Sent: Tuesday, March 3, 2020 6:17 PM >> >> Emulation requiring device model assistance uses a form of instruction >> re-execution, assuming that the second (and any further) pass takes >> exactly the same path. This is a valid

Re: [Xen-devel] [PATCH v5 2/4] x86/HVM: implement memory read caching for insn emulation

2020-03-09 Thread Tian, Kevin
> From: Jan Beulich > Sent: Tuesday, March 3, 2020 6:17 PM > > Emulation requiring device model assistance uses a form of instruction > re-execution, assuming that the second (and any further) pass takes > exactly the same path. This is a valid assumption as far as use of CPU ah, I was not

Re: [Xen-devel] [PATCH v5 2/4] x86/HVM: implement memory read caching for insn emulation

2020-03-03 Thread Durrant, Paul
> -Original Message- > From: Jan Beulich > Sent: 03 March 2020 15:24 > To: Durrant, Paul > Cc: xen-devel@lists.xenproject.org; Kevin Tian ; Wei > Liu ; Paul > Durrant ; Andrew Cooper ; Jun > Nakajima > ; Roger Pau Monné > Subject: RE: [EXTERNAL][PATCH v5 2/4] x86/HVM: implement memory

Re: [Xen-devel] [PATCH v5 2/4] x86/HVM: implement memory read caching for insn emulation

2020-03-03 Thread Durrant, Paul
> -Original Message- > From: Xen-devel On Behalf Of Jan > Beulich > Sent: 03 March 2020 10:17 > To: xen-devel@lists.xenproject.org > Cc: Kevin Tian ; Wei Liu ; Paul Durrant > ; Andrew > Cooper ; Jun Nakajima ; > Roger Pau Monné > > Subject: [EXTERNAL][

Re: [Xen-devel] [PATCH v5 2/4] x86/HVM: implement memory read caching for insn emulation

2020-03-03 Thread Jan Beulich
On 03.03.2020 16:16, Durrant, Paul wrote: >> From: Xen-devel On Behalf Of Jan >> Beulich >> Sent: 03 March 2020 10:17 >> >> --- a/xen/arch/x86/hvm/emulate.c >> +++ b/xen/arch/x86/hvm/emulate.c >> @@ -28,6 +28,19 @@ >> #include >> #include >> >> +struct hvmemul_cache >> +{ >> +/* The

[Xen-devel] [PATCH v5 2/4] x86/HVM: implement memory read caching for insn emulation

2020-03-03 Thread Jan Beulich
Emulation requiring device model assistance uses a form of instruction re-execution, assuming that the second (and any further) pass takes exactly the same path. This is a valid assumption as far as use of CPU registers goes (as those can't change without any other instruction executing in between