From: Andrii Anisov
PPI are pcpu private, so their processing is not concurrent and do not
need pcpu shared flags and correspondent lockings. So avoid odd bits
sets, checks and locks.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/gic.c| 8 ++--
xen/arch/arm/irq.c| 32 +
Julien,
Sorry for bothering you too much.
What about this patch?
--
Sincerely,
Andrii Anisov.
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Hi,
On 12/12/2018 12:37, Andrii Anisov wrote:
Julien,
Sorry for bothering you too much.
What about this patch?
I haven't answered because I am waiting the numbers.
Cheers,
--
Julien Grall
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On 12.12.18 14:46, Julien Grall wrote:
I haven't answered because I am waiting the numbers.
I got it.
But TBM will not show effect of this patch. Even the patch breaks TBM's
functionality because TBM relies on a phys timer interrupt to be assigned to
the domain (go through the spi path).
--
Hi,
On 12/12/2018 12:52, Andrii Anisov wrote:
On 12.12.18 14:46, Julien Grall wrote:
I haven't answered because I am waiting the numbers.
I got it.
But TBM will not show effect of this patch.
If TBM does not show effect, then you need a different benchmark. Probably by
looking at how the
