Re: smmuv1 breakage

On Wed, 23 Jun 2021, Rahul Singh wrote: > Hi Stefano, > > > On 23 Jun 2021, at 9:09 am, Rahul Singh wrote: > > > > Hi Stefano, > > > >> On 22 Jun 2021, at 10:06 pm, Stefano Stabellini > >> wrote: > >> > >> Hi Rahul, > >> > >> Do you have an opinion on how we should move forward on this? > >> >

Re: smmuv1 breakage

Hi Stefano, > On 23 Jun 2021, at 9:09 am, Rahul Singh wrote: > > Hi Stefano, > >> On 22 Jun 2021, at 10:06 pm, Stefano Stabellini >> wrote: >> >> Hi Rahul, >> >> Do you have an opinion on how we should move forward on this? >> >> Do you think it is OK to go for a full revert of "xen/arm: smmuv1

Re: smmuv1 breakage

Hi Stefano, > On 22 Jun 2021, at 10:06 pm, Stefano Stabellini > wrote: > > Hi Rahul, > > Do you have an opinion on how we should move forward on this? > > Do you think it is OK to go for a full revert of "xen/arm: smmuv1: > Intelligent SMR allocation" or do you think it is best to go with an

Re: smmuv1 breakage

Hi Rahul, Do you have an opinion on how we should move forward on this? Do you think it is OK to go for a full revert of "xen/arm: smmuv1: Intelligent SMR allocation" or do you think it is best to go with an alternative fix? If so, do you have something in mind? On Tue, 15 Jun 2021, Stefano St

Re: smmuv1 breakage

On Tue, 15 Jun 2021, Rahul Singh wrote: > Hi Stefano > > > On 15 Jun 2021, at 3:21 am, Stefano Stabellini > > wrote: > > > > Hi Rahul, > > > > Unfortunately, after bisecting, I discovered a few more breakages due to > > your smmuv1 series (commits e889809b .. 3e6047ddf) on Xilinx ZynqMP. I > >

Re: smmuv1 breakage

Hi Stefano > On 15 Jun 2021, at 3:21 am, Stefano Stabellini wrote: > > Hi Rahul, > > Unfortunately, after bisecting, I discovered a few more breakages due to > your smmuv1 series (commits e889809b .. 3e6047ddf) on Xilinx ZynqMP. I > attached the DTB as reference. Please note that I made sure to

smmuv1 breakage

Hi Rahul, Unfortunately, after bisecting, I discovered a few more breakages due to your smmuv1 series (commits e889809b .. 3e6047ddf) on Xilinx ZynqMP. I attached the DTB as reference. Please note that I made sure to cherry-pick "xen/arm: smmuv1: Revert associating the group pointer with the S2CR"