Typical PCI devices have many sources of interrupts (some level, some edge
triggered) normally all routed through PIN A.
When writing an RTDM pci driver for one of these devices, how does the
microkernel manage the edge interrupts?
I am looking at some traces where the CPU seems to be interrupt
On 07/17/2012 04:57 PM, Jorge Ramirez Ortiz, HCL Europe wrote:
> Typical PCI devices have many sources of interrupts (some level, some edge
> triggered) normally all routed through PIN A.
AFAIC, PCI interrupts are *always* level sensitive.
> When writing an RTDM pci driver for one of these devic
On 2012-07-17 17:00, Wolfgang Grandegger wrote:
> On 07/17/2012 04:57 PM, Jorge Ramirez Ortiz, HCL Europe wrote:
>> Typical PCI devices have many sources of interrupts (some level, some edge
>> triggered) normally all routed through PIN A.
>
> AFAIC, PCI interrupts are *always* level sensitive.
bottom of the thread...]
From: Jan Kiszka [jan.kis...@siemens.com]
Sent: 17 July 2012 16:02
To: Wolfgang Grandegger; Jorge Ramirez Ortiz, HCL Europe
Cc: xenomai@xenomai.org
Subject: Re: [Xenomai] Edge interrupts on PCI drivers
On 2012-07-17 17:00, Wolfgang
