On 03/28/2012 05:53 PM, Makarand Pradhan wrote:
Hi All,
I am working with MPC8360, Linux 3.0.0, Xenomai 2.6.
I am experiencing delays as high as 250ms in processing interrupt 43
(2b). Interrupt 43 indicates that the power quicc engine has
transmitted/received a frame. This interrupt is being ha
Hi Philippe,
On 28/03/12 12:17 PM, Philippe Gerum wrote:
The log says your code wants to control when the IRQ is enabled again,
by calling rt_intr_enable() from userland. I guess you are setting
I_NOAUTOENA too. Correct?
That is correct. I_NOAUTOENA is used in rt_intr_create. Otherwise the
le
On 03/28/2012 08:23 PM, Makarand Pradhan wrote:
Hi Philippe,
On 28/03/12 12:17 PM, Philippe Gerum wrote:
The log says your code wants to control when the IRQ is enabled again,
by calling rt_intr_enable() from userland. I guess you are setting
I_NOAUTOENA too. Correct?
That is correct. I_NOAUT
Hi Philippe,
We have found that the problem is that the interrupt is unexpectedly
held masked at the IPIC level for a long time. Please find the trace below:
2552 :| + func -544130.590
qe_ic_cascade_low_ipic+0x8 (__ipipe_ack_irq+0x2c)
2553 :| + func -54412
