The constants are written directly into a buffer object shared with the
card and we "forget" to swap them. This patch fixes it by doing the swap
in evergreen_set_alu_consts() in-place (ie, it modifies the buffer),
which should be fine with the way we use it in the ddx.
This makes everything work fine on my caicos card on a G5 including some
quik tests with Xv, gnome3 shell, etc...
Thanks a lot to Jerome Glisse for holding my hand through debugging that
(and finding the actual bug).
Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org>
---
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index 5c95e20..83320c8 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -479,6 +479,17 @@ evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t
*const_conf, uint32_t
if (size == 0)
size = 1;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {
+ uint32_t count = size << 4, *p = const_conf->cpu_ptr;
+
+ while(count--) {
+ *p = cpu_to_le32(*p);
+ p++;
+ }
+ }
+#endif
+
/* flush SQ cache */
evergreen_cp_set_surface_sync(pScrn, SH_ACTION_ENA_bit,
const_conf->size_bytes,
const_conf->const_addr,
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 6becbb3..603d854 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -172,6 +172,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm,
Pixel fg)
ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
ps_const_conf.bo = accel_state->cbuf.vb_bo;
ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_offset;
+ ps_const_conf.cpu_ptr = (uint32_t *)(char *)ps_alu_consts;
if (accel_state->dst_obj.bpp == 16) {
r = (fg >> 11) & 0x1f;
g = (fg >> 5) & 0x3f;
@@ -1320,6 +1321,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr
pSrcPicture,
vs_const_conf.bo = accel_state->cbuf.vb_bo;
vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_offset;
+ vs_const_conf.cpu_ptr = (uint32_t *)(char *)cbuf;
EVERGREENXFormSetup(pSrcPicture, pSrc, 0, cbuf);
if (pMask)
EVERGREENXFormSetup(pMaskPicture, pMask, 1, cbuf);
diff --git a/src/evergreen_state.h b/src/evergreen_state.h
index 40fec22..5fd85f8 100644
--- a/src/evergreen_state.h
+++ b/src/evergreen_state.h
@@ -120,6 +120,7 @@ typedef struct {
int size_bytes;
uint64_t const_addr;
struct radeon_bo *bo;
+ uint32_t *cpu_ptr;
} const_config_t;
/* Vertex buffer / vtx resource */
diff --git a/src/evergreen_textured_videofuncs.c
b/src/evergreen_textured_videofuncs.c
index 6200cdc..d27a02a 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -449,6 +449,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
ps_const_conf.bo = accel_state->cbuf.vb_bo;
ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_offset;
+ ps_const_conf.cpu_ptr = (uint32_t *)(char *)ps_alu_consts;
ps_alu_consts[0] = off[0];
ps_alu_consts[1] = off[1];
@@ -474,6 +475,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
vs_const_conf.bo = accel_state->cbuf.vb_bo;
vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_offset;
+ vs_const_conf.cpu_ptr = (uint32_t *)(char *)vs_alu_consts;
vs_alu_consts[0] = 1.0 / pPriv->w;
vs_alu_consts[1] = 1.0 / pPriv->h;
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