> > Wouldn't it be better to invest more time in support for existing
> > logic analyzers? Features like memory compression support for
> > pulseview would help the project a lot more in my opinion.
>
> No, because frankly, what's currently out there is crap. 

My 2 cents (for what its worth): support more 32-channel (or higher) logic 
analyzers.  Sigrok has good support in the 8- to 16-channel range but only a 
handful beyond that (and some of those are no longer for sale).  As a user, 
16-channel and lower is useless for my purposes (a used HP 16500C was almost 
chosen but Sigrok + LWLA1034 won).

Whether this means supporting existing LAs or supporting BitMagic, for the 
end-user it doesn't matter which option.  For Open Source's sake, I prefer 
BitMagic.  Side note: I agree, why hasn't someone already built an LA that uses 
USB 3's massive bandwidth??

Another feature I'd like to see is being able to save the channel 
configurations / assignments to a file.  As the the number of channels grow, it 
becomes more time-consuming and error-prone to re-assign channels when 
re-launching PulseView.  Note: my PulseView install is very out-of-date so this 
feature may have already been added; I plan to update when I finish setting up 
my new laptop.

________________________________________
From: Soeren Apel <soe...@apelpie.net>
Sent: Friday, January 26, 2018 3:22 AM
To: Vlad Ivanov; Chris Obbard
Cc: sigrok-devel@lists.sourceforge.net
Subject: Re: [sigrok-devel] (no subject)

Hello folks,

> Wouldn't it be better to invest more time in support for existing
> logic analyzers? Features like memory compression support for
> pulseview would help the project a lot more in my opinion.

No, because frankly, what's currently out there is crap.

Using an FPGA as a front-end and RAM interface to shovel the data
into, then pushing the data over a slow serial (UART or USB2)
interface into the PC when the RAM is full and acquisition has stopped
is a concept that worked well for years but it's totally outdated
now.

Streaming is where it's at, and that's why the FX2 is awesome.
But then there's the 24MHz limit, and to pass that, an FPGA is needed
again, creating the problem of firmware upload and a comm protocol.

I'd much prefer using USB3 (with or without an FPGA), which imo is
the holy grail as of now. It still boggles my mind that it takes so
long for someone to actually do it. Heck, Cypress even has a datapump
demo firmware for the FX3 written already. It's all there.

https://eur02.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fesden%2Fbitmagic&data=02%7C01%7C%7C6a6cd61064944843ae2a08d564af3add%7C84df9e7fe9f640afb435aaaaaaaaaaaa%7C1%7C0%7C636525626125355741&sdata=9KWSGmxLCb4j9YnfFCzJWgqccM38D2WcSj7CJ%2BfCcLA%3D&reserved=0
 is what I'm betting on because he
has commercial interest. It's obvious that such a design will be
cloned by Chinese vendors, which is both good and bad. Either way,
his design will be open and so will be the sigrok drivers, so feel
free to support him if you wish.


> Keep in mind that designing a device like this and implementing some
> basic functionality as a demonstration is actually the easy part.
> It's just a box that streams some data to PC after all.
> The hard  part is polishing is so it works 99.5% of the time instead
> of 90%, producing it, sourcing components, managing sales and so on.

Nah... 90% of the work is *proving* that it works and writing the
sigrok driver. At that point, the floodgates will open and it will be
cloned since others already did the legwork for the Chinese vendors.
They have software to ship with their hardware, the firmware is
available, the hardware is easy to clone and there's huge demand.
It would be a complete heyday.

Which, btw, is the one single reason why I think no one wanted to do
it yet.

-Soeren


>
> 26.01.2018, 11:34, "Chris Obbard" <ch...@64studio.com>:
> >
> > >
> > >  It's been a while and I'm not aware of an "official" collection
> > > of
> > >  events, but here's a list of the things I remember:
> > >
> > >  -) Initially, they created a kickstarter [1]. You can see their
> > > claims
> > >  of open hardware and open software. Initially, they had removed
> > > all
> > >  traces of sigrok/PV from the UI, even though they did retain
> > > certain
> > >  copyright notices and sigrok references in the source. [2]
> > >
> > >  -) From what I remember, Uwe made them aware of this but it
> > > wasn't
> > >  until mid-2017 until they changed it. [3]
> > >
> > >  -) Their initial firmware was based on fx2lafw but they removed
> > > all
> > >  copyrights and fx2lafw/sigrok references in their initial commit
> > > [4].
> > >  Only after Uwe made them aware that this violates the GPL, they
> > >  added sigrok references and reverted the copyright messages [5].
> > >
> > >  -) The DSLogic-fw repo on github contains an old firmware that
> > > is
> > >  no longer used. They claim to now supply firmware (in binary
> > > form)
> > >  that is no longer based on fx2lafw, though they never made the
> > > source
> > >  available. We are uncertain whether they truly rewrote the
> > > firmware
> > >  from scratch or whether they simply smartened up and mangled the
> > > code.
> > >  They're not giving us much to work with here, so it's easy to
> > > assume
> > >  the latter.
> > >
> > >  -) Their git commits almost always consist of a LOT of changes
> > >  squashed into a single commit. Intention is unclear but I
> > > suspect
> > >  that that's their way of complying with the GPL while preventing
> > >  anyone from really taking back from the project.
> > >
> > >  I don't remember whether their kickstarter initially mentioned
> > > sigrok
> > >  or whether they edited the text later on to include it. Either
> > > way,
> > >  it is obvious that their intention never was to give back, only
> > > to take
> > >  and make money off of our work. That's what I'm so sore about.
> >
> > This really is a shame. It's not a good business plan to rip off
> > open
> > source projects... It seemed like a good contender, too.
> >
> > So this goes onto my next question, who's interested in designing
> > an
> > open-source logic-analyser with good chassis, cables etc for
> > Sigrok?
> >
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