Hi all,
I'm Seongil O under MS. degree course in SNU. Today, I downloaded and
installed FLEXUS, and then ran test-app.
Since I want to run splash2 benchmark with
flexus-CMP.L2SharedNUCA.Inorder-x86-iface-gcc, I modified
user-postload.simics. However I ecountered following error messages.
103 <MemoryMapImpl.cpp:299> {0}- <undefined> Assertion failed:
((!(!theMapLoaded))) : Attempted to load page map twice
(flexus_state_in/page_map.out)
Abort (SIGABRT) in main thread
The simulation state has been corrupted. Simulation cannot continue.
Please restart Simics.
My user-postload.simics and simulation log are as follows.
=== user-postload.simics ===
### ufetch
# Fetch [timing]
flexus.set "-fetch:stalli" "true"
flexus.set "-fetch:icachelinesize" "64"
### L1d
flexus.set "-L1d:bsize" "64" #
"Block size" (BlockSize)
flexus.set "-L1d:level" "eL1" #
"CacheLevel" (CacheLevel)
flexus.set "-L1d:allow_evict_clean" "1" #
"Cause the cache to evict clean blocks" (EvictClean)
flexus.set "-L1d:array_config"
"STD:size=32768:assoc=2:repl=LRU" # "Configuration of cache array
(STD:sets=1024:assoc=16:repl=LRU" (ArrayConfiguration)
flexus.set "-L1d:banks" "1" #
"number of banks on the data and tag arrays" (Banks)
flexus.set "-L1d:bustime_data" "2" #
"Bus transfer time - data" (BusTime_Data)
flexus.set "-L1d:bustime_nodata" "1" #
"Bus transfer time - no data" (BusTime_NoData)
flexus.set "-L1d:cache_type"
"InclusiveMESI:snoop_lru=false" # "Type of cache (InclusiveMOESI)"
(CacheType)
flexus.set "-L1d:cores" "1" #
"Number of cores" (Cores)
flexus.set "-L1d:data_issue_lat" "1" #
"Minimum delay between issues to data pipeline" (DataIssueLatency)
flexus.set "-L1d:data_lat" "1" #
"Total latency of data pipeline" (DataLatency)
flexus.set "-L1d:dup_tag_issue_lat" "1" #
"Minimum delay between issues to tag pipeline" (TagIssueLatency)
flexus.set "-L1d:eb" "8" #
"Number of Evict Buffer entries" (EvictBufferSize)
flexus.set "-L1d:evict_on_snoop" "0" #
"Send evictions on Snoop channel" (EvictOnSnoop)
flexus.set "-L1d:fast_evict_clean" "0" #
"Send clean evicts without reserving data bus" (FastEvictClean)
flexus.set "-L1d:maf" "8" #
"Number of MAF entries" (MAFSize)
flexus.set "-L1d:maf_targets" "0" #
"Number of MAF targets per request" (MAFTargetsPerRequest)
flexus.set "-L1d:no_bus" "0" #
"No bus model (i.e., infinite BW, no latency)" (NoBus)
flexus.set "-L1d:ports" "2" #
"Number of ports on data and tag arrays" (Ports)
flexus.set "-L1d:pre_queue_size" "4" #
"Size of input arbitration queues" (PreQueueSizes)
flexus.set "-L1d:probe_fetchmiss" "0" #
"Probe hierarchy on Ifetch miss" (ProbeFetchMiss)
flexus.set "-L1d:queue_size" "8" #
"Size of input and output queues" (QueueSizes)
flexus.set "-L1d:snoops" "8" #
"Number of Snoop Buffer entries" (SnoopBufferSize)
flexus.set "-L1d:tag_lat" "1" #
"Total latency of tag pipeline" (TagLatency)
flexus.set "-L1d:trace_address" "0" #
"Address to initiate tracing" (TraceAddress)
flexus.set "-L1d:use_reply_channel" "1" #
"Separate Reply and Snoop channels on BackSide" (UseReplyChannel)
flexus.set "-L1d:text_flexpoints" "0"
flexus.set "-L1d:gzip_flexpoints" "1"
### L1i
flexus.set "-L1i:bsize" "64" #
"Block size" (BlockSize)
flexus.set "-L1i:level" "eL1" #
"CacheLevel" (CacheLevel)
flexus.set "-L1i:allow_evict_clean" "1" #
"Cause the cache to evict clean blocks" (EvictClean)
flexus.set "-L1i:array_config"
"STD:size=32768:assoc=2:repl=LRU" # "Configuration of cache array
(STD:sets=1024:assoc=16:repl=LRU" (ArrayConfiguration)
flexus.set "-L1i:banks" "1" #
"number of banks on the data and tag arrays" (Banks)
flexus.set "-L1i:bustime_data" "2" #
"Bus transfer time - data" (BusTime_Data)
flexus.set "-L1i:bustime_nodata" "1" #
"Bus transfer time - no data" (BusTime_NoData)
flexus.set "-L1i:cache_type"
"InclusiveMESI:snoop_lru=false" # "Type of cache (InclusiveMOESI)"
(CacheType)
flexus.set "-L1i:cores" "1" #
"Number of cores" (Cores)
flexus.set "-L1i:data_issue_lat" "1" #
"Minimum delay between issues to data pipeline" (DataIssueLatency)
flexus.set "-L1i:data_lat" "1" #
"Total latency of data pipeline" (DataLatency)
flexus.set "-L1i:dup_tag_issue_lat" "1" #
"Minimum delay between issues to tag pipeline" (TagIssueLatency)
flexus.set "-L1i:eb" "8" #
"Number of Evict Buffer entries" (EvictBufferSize)
flexus.set "-L1i:evict_on_snoop" "0" #
"Send evictions on Snoop channel" (EvictOnSnoop)
flexus.set "-L1i:fast_evict_clean" "0" #
"Send clean evicts without reserving data bus" (FastEvictClean)
flexus.set "-L1i:maf" "8" #
"Number of MAF entries" (MAFSize)
flexus.set "-L1i:maf_targets" "0" #
"Number of MAF targets per request" (MAFTargetsPerRequest)
flexus.set "-L1i:no_bus" "0" #
"No bus model (i.e., infinite BW, no latency)" (NoBus)
flexus.set "-L1i:ports" "2" #
"Number of ports on data and tag arrays" (Ports)
flexus.set "-L1i:pre_queue_size" "4" #
"Size of input arbitration queues" (PreQueueSizes)
flexus.set "-L1i:probe_fetchmiss" "0" #
"Probe hierarchy on Ifetch miss" (ProbeFetchMiss)
flexus.set "-L1i:queue_size" "8" #
"Size of input and output queues" (QueueSizes)
flexus.set "-L1i:snoops" "8" #
"Number of Snoop Buffer entries" (SnoopBufferSize)
flexus.set "-L1i:tag_lat" "1" #
"Total latency of tag pipeline" (TagLatency)
flexus.set "-L1i:trace_address" "0" #
"Address to initiate tracing" (TraceAddress)
flexus.set "-L1i:use_reply_channel" "1" #
"Separate Reply and Snoop channels on BackSide" (UseReplyChannel)
flexus.set "-L1i:text_flexpoints" "1"
flexus.set "-L1i:gzip_flexpoints" "0"
### L2
flexus.set "-L2:bsize" "64" #
"Block size" (BlockSize)
flexus.set "-L2:level" "eL2" #
"CacheLevel" (CacheLevel)
flexus.set "-L2:allow_evict_clean" "0" #
"Cause the cache to evict clean blocks" (EvictClean)
flexus.set "-L2:array_config"
"STD:total_sets=8192:assoc=16:repl=LRU" # "Configuration of cache
array (STD:sets=1024:assoc=16:repl=LRU" (ArrayConfiguration)
flexus.set "-L2:bank_interleaving" "64" #
"interleaving between directory banks (64 bytes)" (BankInterleaving)
flexus.set "-L2:banks" "1" #
"number of directory banks in each group" (Banks)
flexus.set "-L2:cache_eb_size" "16" #
"Number of Evict Buffer entries for the cache" (CacheEvictBufferSize)
flexus.set "-L2:cores" "2" #
"Number of cores" (Cores)
flexus.set "-L2:data_issue_lat" "3" #
"Minimum delay between issues to the data array" (DataIssueLatency)
flexus.set "-L2:data_lat" "8" #
"Total latency of data array lookup" (DataLatency)
flexus.set "-L2:dir_config" "" #
"Configuration of directory array (sets=1024:assoc=16)" (DirectoryConfig)
flexus.set "-L2:dir_eb_size" "16" #
"Number of Evict Buffer entries for the directory" (DirEvictBufferSize)
flexus.set "-L2:dir_issue_lat" "2" #
"Minimum delay between issues to the directory" (DirIssueLatency)
flexus.set "-L2:dir_lat" "2" #
"Total latency of directory lookup" (DirLatency)
flexus.set "-L2:dir_type" "inf" #
"Type of directory (infinite, std, region, etc.)" (DirectoryType)
flexus.set "-L2:group_interleaving" "1024" #
"interleaving between directory bank groups (1024 bytes)"
(GroupInterleaving)
flexus.set "-L2:groups" "1" #
"number of directory bank groups" (Groups)
flexus.set "-L2:maf_size" "64" #
"Number of MAF entries" (MAFSize)
flexus.set "-L2:policy" "NonInclusiveMESI" #
"Coherence policy for higher caches (NonInclusiveMESI)" (Policy)
flexus.set "-L2:queue_size" "16" #
"Size of input and output queues" (QueueSize)
flexus.set "-L2:tag_issue_lat" "2" #
"Minimum delay between issues to the tag array" (TagIssueLatency)
flexus.set "-L2:tag_lat" "4" #
"Total latency of tag array lookup" (TagLatency)
### nic
# MultiNic2 [timing]
flexus.set "-nic:recv-capacity" "4" #
"Recv Queue Capacity" (RecvCapacity)
flexus.set "-nic:send-capacity" "4" #
"Send Queue Capacity" (SendCapacity)
flexus.set "-nic:vc" "3" #
"Virtual channels" (VChannels)
### network
# MemoryNetwork [timing]
flexus.set "-network:nodes" "3" #
"Number of Nodes" (NumNodes)
flexus.set "-network:topology-file" "1x3-torus.topology" #
"Network topology file" (NetworkTopologyFile)
flexus.set "-network:virtual-channels" "3" #
"Number of virtual channels" (VChannels)
### net-mapper
# SplitDestinationMapper [timing]
# flexus.set "-net-mapper:Cores" "1"
# "Number of cores" (Cores)
flexus.set "-net-mapper:Cores" "2" #
"Number of cores" (Cores)
flexus.set "-net-mapper:DirInterleaving" "64" #
"Interleaving between directories (in bytes)" (DirInterleaving)
flexus.set "-net-mapper:DirLocation" "Distributed" #
"Directory location (Distributed|AtMemory)" (DirLocation)
flexus.set "-net-mapper:DirXORShift" "-1" #
"XOR high order bits after shifting this many bits when calculating
directory index" (DirXORShift)
# flexus.set "-net-mapper:Directories" "1"
# "Number of directories" (Directories)
flexus.set "-net-mapper:Directories" "2" #
"Number of directories" (Directories)
flexus.set "-net-mapper:LocalDir" "0" #
"Treate directory as always being local to the requester" (LocalDir)
flexus.set "-net-mapper:MemControllers" "1" #
"Number of memory controllers" (MemControllers)
flexus.set "-net-mapper:MemInterleaving" "64" #
"Interleaving between memory controllers (in bytes)" (MemInterleaving)
flexus.set "-net-mapper:MemLocation" "0" #
"Memory controller locations (ex: '8,15,24,31,32,39,48,55')"
(MemLocation)
flexus.set "-net-mapper:MemReplyToDir" "1" #
"Send memory replies to the directory (instead of original requester)"
(MemReplyToDir)
flexus.set "-net-mapper:MemXORShift" "-1" #
"XOR high order bits after shifting this many bits when calculating
memory index" (MemXORShift)
flexus.set "-net-mapper:TwoPhaseWB" "0" #
"2 Phase Write-Back sends NAcks to requester, not directory" (TwoPhaseWB)
### memory
# MemoryLoopback [timing]
flexus.set "-memory:UseFetchReply" "1" #
"Send FetchReply in response to FetchReq (instead of MissReply)"
(UseFetchReply)
flexus.set "-memory:max_requests" "64" #
"Maximum requests queued in loopback" (MaxRequests)
flexus.set "-memory:time" "150" #
"Access time" (Delay)
### memory-map
# MemoryMap [timing]
flexus.set "-memory-map:nodes" "1" #
"Number of Nodes" (NumNodes)
flexus.set "-memory-map:page_map" "1" #
"Load Page Map on start" (ReadPageMap)
flexus.set "-memory-map:pagesize" "8192" #
"Page size in bytes (used by statistics only)" (PageSize)
flexus.set "-memory-map:round_robin" "1" #
"Use static round-robin page allocation" (RoundRobin)
flexus.set "-memory-map:write_page_map" "1" #
"Write page map as pages are created" (CreatePageMap)
### magic-break
# MagicBreak MagicBreak [timing+trace]
flexus.set "-magic-break:ckpt_cycle" "0" #
"# of cycles between checkpoints." (CkptCycleInterval)
flexus.set "-magic-break:ckpt_cycle_name" "0" #
"Base cycle # from which to build checkpoint names." (CkptCycleName)
flexus.set "-magic-break:ckpt_iter" "0" #
"Checkpoint simulation when CPU 0 reaches each iteration."
(CheckpointOnIteration)
flexus.set "-magic-break:ckpt_trans" "-1" #
"Quiesce and save every X transactions. -1 disables"
(CheckpointEveryXTransactions)
flexus.set "-magic-break:end_iter" "-1" #
"Terminate simulation when CPU 0 reaches iteration. -1 disables"
(TerminateOnIteration)
flexus.set "-magic-break:end_trans" "-1" #
"Terminate simulation after ## transactions. -1 disables"
(TerminateOnTransaction)
flexus.set "-magic-break:first_trans" "0" #
"Transaction number for first transaction." (FirstTransactionIs)
flexus.set "-magic-break:iter" "0" #
"Enable Iteration Counts" (EnableIterationCounts)
flexus.set "-magic-break:min_cycle" "0" #
"Minimum number of cycles to run when TerminateOnTransaction is
enabled." (CycleMinimum)
flexus.set "-magic-break:stats_trans" "1000" #
"Statistics interval on ## transactions. -1 disables"
(TransactionStatsInterval)
flexus.set "-magic-break:stop_cycle" "0" #
"Cycle on which to halt simulation." (StopCycle)
flexus.set "-magic-break:stop_on_magic" "-1" #
"Terminate simulation on a specific magic breakpoint"
(TerminateOnMagicBreak)
flexus.set "-magic-break:trans" "1" #
"Enable Transaction Counts" (EnableTransactionCounts)
flexus.set "-feeder:trace-file" ""
flexus.set "-feeder:use-trace" "false"
flexus.set "-feeder:stall-cap" "5000"
flexus.set "-execute:sb" "32"
flexus.set "-execute:rob" "96"
flexus.set "-execute:lsq" "64"
flexus.set "-execute:memory" "32"
flexus.set "-execute:sc" "1"
flexus.set "-execute:stpf" "false"
flexus.set "-execute:MaxSpinLoads" "3"
=== simulation log ===
Image memory limited to 1 GB
Opening debug output file: debug.out
Opening debug output file: stats.out
Opening debug output file: trace.out
Successfully parsed debug configurations from debug.cfg
Initializing Flexus::ConfigurationManager...done
Initializing Flexus::ComponentManager...done
Entered init_local
Flexus (C) 2006-2010 The SimFlex Project
Eric Chung, Michael Ferdman, Brian Gold, Nikos Hardavellas, Jangwook Kim,
Ippokratis Pandis, Minglong Shao, Jared Smolens, Stephen Somogyi,
Evangelos Vlachos, Thomas Wenisch, Roland Wunderlich
Anastassia Ailamaki, Babak Falsafi and James C. Hoe.
Flexus Simics simulator - Built as CMP.L2SharedNUCA.Inorder v1.0
1 <startup.cpp:121> {0}- Initializing Flexus.
2 <ComponentManager.cpp:80> {0}- Instantiating system with a width
factor of: 2
3 <InorderSimicsFeederImpl.cpp:159> {0}- Initializing
InorderSimicsFeeder with 2 cpus.
4 <InorderSimicsFeederImpl.cpp:287> {0}- sys-feeder Initializing
InorderSimicsFeeder.
5 <mai_api.cpp:273> {0}- Searching 2 cpus.
6 <mai_api.cpp:277> {0}- Processor 0: cpu0 - CPU 0
7 <mai_api.cpp:296> {0}- Found CPU: '' - 0
8 <mai_api.cpp:277> {0}- Processor 1: cpu1 - CPU 1
9 <mai_api.cpp:296> {0}- Found CPU: '' - 1
10 <mai_api.cpp:313> {0}- Found 2 Flexus CPUs and 0 Client CPUs in 0 VMs
11 <mai_api.cpp:352> {0}- VMS per row = 1, CPVM = 2, NVMR = 2, NumRow = 2
12 <mai_api.cpp:379> {0}- theProcMap[0] = (0, 0) (abs_index = 0)
13 <mai_api.cpp:379> {0}- theProcMap[1] = (1, 0) (abs_index = 1)
14 <mai_api.cpp:384> {0}- Finished creating Processor Mapper.
15 <InorderSimicsFeederImpl.cpp:292> {0}- ProcessorMapper found 2 CPUs
for Flexus.
16 <Cache.hpp:93> {0}- L1d port FrontSideOut_I is not wired
17 <Cache.hpp:93> {0}- L1d port BackSideOut_Prefetch is not wired
18 <Cache.hpp:93> {0}- L1d port FrontSideOut_I is not wired
19 <Cache.hpp:93> {0}- L1d port BackSideOut_Prefetch is not wired
20 <Cache.hpp:93> {0}- L1i port FrontSideOut_D is not wired
21 <Cache.hpp:93> {0}- L1i port BackSideOut_Prefetch is not wired
22 <Cache.hpp:93> {0}- L1i port FrontSideOut_D is not wired
23 <Cache.hpp:93> {0}- L1i port BackSideOut_Prefetch is not wired
24 <wiring.cpp:101> {0}- initializing Parameters...
Warning: The 'flexus-CMP.L2SharedNUCA.Inorder-x86-iface-gcc' module
unexpectedly defined the 'Flexus' class
Warning: The 'flexus-CMP.L2SharedNUCA.Inorder-x86-iface-gcc' module
unexpectedly defined the 'SimicsInterface' class
Warning: The 'flexus-CMP.L2SharedNUCA.Inorder-x86-iface-gcc' module
unexpectedly defined the 'InOrderFeeder' class
25 <configuration.hpp:193> {0}- Bad Lexical Cast attempting to set
dynamic parameter.
25 <configuration.hpp:193> {0}- Bad Lexical Cast attempting to set
dynamic parameter.
WARNING: Unable to set parameter CacheLevel to eL1
26 <configuration.hpp:193> {0}- Bad Lexical Cast attempting to set
dynamic parameter.
26 <configuration.hpp:193> {0}- Bad Lexical Cast attempting to set
dynamic parameter.
WARNING: Unable to set parameter CacheLevel to eL1
27 <configuration.hpp:193> {0}- Bad Lexical Cast attempting to set
dynamic parameter.
27 <configuration.hpp:193> {0}- Bad Lexical Cast attempting to set
dynamic parameter.
WARNING: Unable to set parameter CacheLevel to eL2
28 <flexus.cpp:388> {0}- Set region interval to : 50000
28 <flexus.cpp:388> {0}- Set region interval to : 50000
29 <flexus.cpp:535> {0}- Loading Flexus state from subdirectory
flexus_state_in
29 <flexus.cpp:535> {0}- Loading Flexus state from subdirectory
flexus_state_in
30 <ComponentManager.cpp:95> {0}- Initalizing components...
30 <ComponentManager.cpp:95> {0}- Initalizing components...
31 <ComponentManager.cpp:99> {0}- Initalizing sys-white-box
31 <ComponentManager.cpp:99> {0}- Initalizing sys-white-box
32 <ComponentManager.cpp:99> {0}- Initalizing sys-feeder
32 <ComponentManager.cpp:99> {0}- Initalizing sys-feeder
33 <InorderSimicsFeederImpl.cpp:274> {0}- sys-feeder Using new
scheduling mechanism.
33 <InorderSimicsFeederImpl.cpp:274> (feeder[<undefined>]) {0}- Using
new scheduling mechanism.
34 <ComponentManager.cpp:99> {0}- Initalizing 00-L1d
34 <ComponentManager.cpp:99> {0}- Initalizing 00-L1d
35 <ComponentManager.cpp:99> {0}- Initalizing 01-L1d
35 <ComponentManager.cpp:99> {0}- Initalizing 01-L1d
36 <ComponentManager.cpp:99> {0}- Initalizing 00-L1i
36 <ComponentManager.cpp:99> {0}- Initalizing 00-L1i
37 <ComponentManager.cpp:99> {0}- Initalizing 01-L1i
37 <ComponentManager.cpp:99> {0}- Initalizing 01-L1i
38 <ComponentManager.cpp:99> {0}- Initalizing 00-fetch
38 <ComponentManager.cpp:99> {0}- Initalizing 00-fetch
39 <IFetchImpl.cpp:101> {0}- 00-fetch StallInstructions: 1
39 <IFetchImpl.cpp:101> {0}- StallInstructions: 1
40 <ComponentManager.cpp:99> {0}- Initalizing 01-fetch
40 <ComponentManager.cpp:99> {0}- Initalizing 01-fetch
41 <IFetchImpl.cpp:101> {0}- 01-fetch StallInstructions: 1
41 <IFetchImpl.cpp:101> {0}- StallInstructions: 1
42 <ComponentManager.cpp:99> {0}- Initalizing 00-execute
42 <ComponentManager.cpp:99> {0}- Initalizing 00-execute
43 <ExecuteImpl.cpp:319> {0}- 00-execute EX initalized
43 <ExecuteImpl.cpp:319> {0}- EX initalized
44 <ExecuteImpl.cpp:322> {0}- 00-execute Sequential Consistency Enabled
44 <ExecuteImpl.cpp:322> {0}- Sequential Consistency Enabled
45 <ComponentManager.cpp:99> {0}- Initalizing 01-execute
45 <ComponentManager.cpp:99> {0}- Initalizing 01-execute
46 <ExecuteImpl.cpp:319> {0}- 01-execute EX initalized
46 <ExecuteImpl.cpp:319> {0}- EX initalized
47 <ExecuteImpl.cpp:322> {0}- 01-execute Sequential Consistency Enabled
47 <ExecuteImpl.cpp:322> {0}- Sequential Consistency Enabled
48 <ComponentManager.cpp:99> {0}- Initalizing 00-bpwarm
48 <ComponentManager.cpp:99> {0}- Initalizing 00-bpwarm
49 <ComponentManager.cpp:99> {0}- Initalizing 01-bpwarm
49 <ComponentManager.cpp:99> {0}- Initalizing 01-bpwarm
50 <ComponentManager.cpp:99> {0}- Initalizing 00-L2
50 <ComponentManager.cpp:99> {0}- Initalizing 00-L2
51 <CMPCacheImpl.cpp:97> {0}- GroupInterleaving = 1024
51 <CMPCacheImpl.cpp:97> {0}- GroupInterleaving = 1024
52 <CMPCacheController.cpp:113> {0}- GI = 1024, 1024
52 <CMPCacheController.cpp:113> {0}- GI = 1024, 1024
53 <NonInclusiveMESIPolicy.cpp:102> {0}- GI = 1024
53 <NonInclusiveMESIPolicy.cpp:102> {0}- GI = 1024
54 <NonInclusiveMESIPolicy.cpp:83> {0}- GI = 1024
54 <NonInclusiveMESIPolicy.cpp:83> {0}- GI = 1024
55 <StdArray.hpp:430> {0}- theGroupInterleaving = 1024
55 <StdArray.hpp:430> {0}- theGroupInterleaving = 1024
56 <StdArray.hpp:540> {0}- blockOffsetBits = 6, indexBits = 13,
bankBits = 0, bankInterleavingBits = 6, groupBits = 0,
groupInterleavingBits = 10, lowBits = 0, midBits = 4, highBits = 9,
setLowMask = 0, setMidMask = f, setHighMask = 1ff0, setLowShift = 6,
setMidShift = 6, setHighShift = 6, theBankMask = 0, theBankShift = 6,
theGroupMask = 0, theGroupShift = 10
56 <StdArray.hpp:540> {0}- blockOffsetBits = 6, indexBits = 13,
bankBits = 0, bankInterleavingBits = 6, groupBits = 0,
groupInterleavingBits = 10, lowBits = 0, midBits = 4, highBits = 9,
setLowMask = 0, setMidMask = f, setHighMask = 1ff0, setLowShift = 6,
setMidShift = 6, setHighShift = 6, theBankMask = 0, theBankShift = 6,
theGroupMask = 0, theGroupShift = 10
57 <ComponentManager.cpp:99> {0}- Initalizing 01-L2
57 <ComponentManager.cpp:99> {0}- Initalizing 01-L2
58 <CMPCacheImpl.cpp:97> {0}- GroupInterleaving = 1024
58 <CMPCacheImpl.cpp:97> {0}- GroupInterleaving = 1024
59 <CMPCacheController.cpp:113> {0}- GI = 1024, 1024
59 <CMPCacheController.cpp:113> {0}- GI = 1024, 1024
60 <NonInclusiveMESIPolicy.cpp:102> {0}- GI = 1024
60 <NonInclusiveMESIPolicy.cpp:102> {0}- GI = 1024
61 <NonInclusiveMESIPolicy.cpp:83> {0}- GI = 1024
61 <NonInclusiveMESIPolicy.cpp:83> {0}- GI = 1024
62 <StdArray.hpp:430> {0}- theGroupInterleaving = 1024
62 <StdArray.hpp:430> {0}- theGroupInterleaving = 1024
63 <StdArray.hpp:540> {0}- blockOffsetBits = 6, indexBits = 13,
bankBits = 0, bankInterleavingBits = 6, groupBits = 0,
groupInterleavingBits = 10, lowBits = 0, midBits = 4, highBits = 9,
setLowMask = 0, setMidMask = f, setHighMask = 1ff0, setLowShift = 6,
setMidShift = 6, setHighShift = 6, theBankMask = 0, theBankShift = 6,
theGroupMask = 0, theGroupShift = 10
63 <StdArray.hpp:540> {0}- blockOffsetBits = 6, indexBits = 13,
bankBits = 0, bankInterleavingBits = 6, groupBits = 0,
groupInterleavingBits = 10, lowBits = 0, midBits = 4, highBits = 9,
setLowMask = 0, setMidMask = f, setHighMask = 1ff0, setLowShift = 6,
setMidShift = 6, setHighShift = 6, theBankMask = 0, theBankShift = 6,
theGroupMask = 0, theGroupShift = 10
64 <ComponentManager.cpp:99> {0}- Initalizing 00-nic
64 <ComponentManager.cpp:99> {0}- Initalizing 00-nic
65 <ComponentManager.cpp:99> {0}- Initalizing 01-nic
65 <ComponentManager.cpp:99> {0}- Initalizing 01-nic
66 <ComponentManager.cpp:99> {0}- Initalizing 02-nic
66 <ComponentManager.cpp:99> {0}- Initalizing 02-nic
67 <ComponentManager.cpp:99> {0}- Initalizing 03-nic
67 <ComponentManager.cpp:99> {0}- Initalizing 03-nic
68 <ComponentManager.cpp:99> {0}- Initalizing 04-nic
68 <ComponentManager.cpp:99> {0}- Initalizing 04-nic
69 <ComponentManager.cpp:99> {0}- Initalizing 05-nic
69 <ComponentManager.cpp:99> {0}- Initalizing 05-nic
70 <ComponentManager.cpp:99> {0}- Initalizing sys-network
70 <ComponentManager.cpp:99> {0}- Initalizing sys-network
Attaching node 0 to switch 0:0
Attaching node 1 to switch 0:1
Attaching node 2 to switch 0:2
Attaching switch 0:5 to switch 0:3
Attaching switch 0:6 to switch 0:4
Adding routing table entry: sw 0 -> 0 thru port 0
Adding routing table entry: sw 0 -> 1 thru port 1
Adding routing table entry: sw 0 -> 2 thru port 2
71 <ComponentManager.cpp:99> {0}- Initalizing sys-memory-map
71 <ComponentManager.cpp:99> {0}- Initalizing sys-memory-map
72 <MemoryMapImpl.cpp:302> {0}- Page map file page_map.out found.
Reading contents...
72 <MemoryMapImpl.cpp:302> {0}- Page map file page_map.out found.
Reading contents...
73 <MemoryMapImpl.cpp:321> {0}- Assigned 0 pages.
73 <MemoryMapImpl.cpp:321> {0}- Assigned 0 pages.
74 <ComponentManager.cpp:99> {0}- Initalizing sys-magic-break
74 <ComponentManager.cpp:99> {0}- Initalizing sys-magic-break
75 <ComponentManager.cpp:99> {0}- Initalizing sys-net-mapper
75 <ComponentManager.cpp:99> {0}- Initalizing sys-net-mapper
76 <SplitDestinationMapperImpl.cpp:142> {0}- sys-net-mapper Creating
SplitDestinationMapper with 2 cores, 2 directories, and 1 memory
controllers.
76 <SplitDestinationMapperImpl.cpp:142> {0}- Creating
SplitDestinationMapper with 2 cores, 2 directories, and 1 memory
controllers.
77 <ComponentManager.cpp:128> {0}- Loading state: sys-white-box
77 <ComponentManager.cpp:128> {0}- Loading state: sys-white-box
78 <ComponentManager.cpp:128> {0}- Loading state: sys-feeder
78 <ComponentManager.cpp:128> {0}- Loading state: sys-feeder
79 <ComponentManager.cpp:128> {0}- Loading state: 00-L1d
79 <ComponentManager.cpp:128> {0}- Loading state: 00-L1d
80 <ComponentManager.cpp:128> {0}- Loading state: 01-L1d
80 <ComponentManager.cpp:128> {0}- Loading state: 01-L1d
81 <ComponentManager.cpp:128> {0}- Loading state: 00-L1i
81 <ComponentManager.cpp:128> {0}- Loading state: 00-L1i
82 <ComponentManager.cpp:128> {0}- Loading state: 01-L1i
82 <ComponentManager.cpp:128> {0}- Loading state: 01-L1i
83 <ComponentManager.cpp:128> {0}- Loading state: 00-fetch
83 <ComponentManager.cpp:128> {0}- Loading state: 00-fetch
84 <ComponentManager.cpp:128> {0}- Loading state: 01-fetch
84 <ComponentManager.cpp:128> {0}- Loading state: 01-fetch
85 <ComponentManager.cpp:128> {0}- Loading state: 00-execute
85 <ComponentManager.cpp:128> {0}- Loading state: 00-execute
86 <ComponentManager.cpp:128> {0}- Loading state: 01-execute
86 <ComponentManager.cpp:128> {0}- Loading state: 01-execute
87 <ComponentManager.cpp:128> {0}- Loading state: 00-bpwarm
87 <ComponentManager.cpp:128> {0}- Loading state: 00-bpwarm
88 <BranchPredictor.cpp:1144> {0}- 00-bpwarm loaded branch predictor.
BTB size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
88 <BranchPredictor.cpp:1144> {0}- 00-bpwarm loaded branch predictor.
BTB size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
89 <ComponentManager.cpp:128> {0}- Loading state: 01-bpwarm
89 <ComponentManager.cpp:128> {0}- Loading state: 01-bpwarm
90 <BranchPredictor.cpp:1144> {0}- 01-bpwarm loaded branch predictor.
BTB size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
90 <BranchPredictor.cpp:1144> {0}- 01-bpwarm loaded branch predictor.
BTB size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
91 <ComponentManager.cpp:128> {0}- Loading state: 00-L2
91 <ComponentManager.cpp:128> {0}- Loading state: 00-L2
92 <InfiniteDirectory.hpp:210> {0}- 00-L2 - Directory loading 528 entries.
92 <InfiniteDirectory.hpp:210> {0}- 00-L2 - Directory loading 528 entries.
93 <ComponentManager.cpp:128> {0}- Loading state: 01-L2
93 <ComponentManager.cpp:128> {0}- Loading state: 01-L2
94 <InfiniteDirectory.hpp:210> {0}- 01-L2 - Directory loading 528 entries.
94 <InfiniteDirectory.hpp:210> {0}- 01-L2 - Directory loading 528 entries.
95 <ComponentManager.cpp:128> {0}- Loading state: 00-nic
95 <ComponentManager.cpp:128> {0}- Loading state: 00-nic
96 <ComponentManager.cpp:128> {0}- Loading state: 01-nic
96 <ComponentManager.cpp:128> {0}- Loading state: 01-nic
97 <ComponentManager.cpp:128> {0}- Loading state: 02-nic
97 <ComponentManager.cpp:128> {0}- Loading state: 02-nic
98 <ComponentManager.cpp:128> {0}- Loading state: 03-nic
98 <ComponentManager.cpp:128> {0}- Loading state: 03-nic
99 <ComponentManager.cpp:128> {0}- Loading state: 04-nic
99 <ComponentManager.cpp:128> {0}- Loading state: 04-nic
100 <ComponentManager.cpp:128> {0}- Loading state: 05-nic
100 <ComponentManager.cpp:128> {0}- Loading state: 05-nic
101 <ComponentManager.cpp:128> {0}- Loading state: sys-network
101 <ComponentManager.cpp:128> {0}- Loading state: sys-network
102 <ComponentManager.cpp:128> {0}- Loading state: sys-memory-map
102 <ComponentManager.cpp:128> {0}- Loading state: sys-memory-map
103 <MemoryMapImpl.cpp:299> {0}- <undefined> Assertion failed:
((!(!theMapLoaded))) : Attempted to load page map twice
(flexus_state_in/page_map.out)
Abort (SIGABRT) in main thread
The simulation state has been corrupted. Simulation cannot continue.
Please restart Simics.
