Hi Song,
First, one question: are you using different cache block sizes for the
different levels of cache? At the moment the cache hierarchy does not
support different cache block sizes at different levels, and I can think
of one way that might produce the error you're seeing. If that's not the
case, keep reading.
The message you're seeing indicates that the shared cache received an
UpgradeAck for a WriteRequest. The sequence of messages should normally
be one of the following:
Normal Case:
requesting L1 sends Upgrade to L2
L2 sends MissNotify to requesting L1 and Invalidates to other L1s
L1s perform Invalidates and send InvalidateAcks to requesting L1
requesting L1 sends UpgradeAck to L2
Fast Case:
requesting L1 sends Upgrade to L2
L2 sends UpgradeReply to L1
L1 sends UpgradeAck to L2
Race Case:
L1-a sends Write to L2
L1-b sends Upgrade to L2
L2 receives Write from L1-a and sends invalidates to L1-b and any other
sharers
L2 receives Upgrade from L1-b, sees that the block has been invalidated,
and silently promotes the request to a Write
L1-a's Write completes and L1-a sends WriteAck to L2
L2 receives WriteAck and processes L1-b's request which is now a Write
To see exactly what happened, you should re-run your simulation and turn
on debugging messages part way through. The error occurs at cycle 51001,
so if you run for 50000 cycles then run the command
flexus.debug-set-severity "iface"
then keep running, you should see a dump of all of the debug messages.
You can then extract all the debug statements for the address in
question and see what exactly might have happened. If you email the list
with those statements, we should be able to resolve your problem.
Jason
On 04/04/2011 4:12 PM, Song Liu wrote:
Another error message comes with same config but different flexpoints.
180<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction
ignored. So far 1 instructions have been ignored on cpu2
181<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction
ignored. So far 2 instructions have been ignored on cpu2
182<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction
ignored. So far 3 instructions have been ignored on cpu2
183<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction
ignored. So far 4 instructions have been ignored on cpu2
184<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction
ignored. So far 5 instructions have been ignored on cpu2
185<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction
ignored. So far 6 instructions have been ignored on cpu2
186<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction
ignored. So far 7 instructions have been ignored on cpu2
187<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction
ignored. So far 8 instructions have been ignored on cpu2
188<NonInclusiveMESIPolicy.cpp:1233> {51001}-<undefined> Assertion
failed: ((!(maf->transport()[MemoryMessageTag]->type() ==
MemoryMessage::UpgradeReq))) : Matching MAF is not an Upgrade. MAF =
MemoryMessage[Write Request]: Addr:0xp:0003bdc80 Size:0 Serial: 24140
Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack reply =
MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 24221
Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack
Song
On Thu, Mar 31, 2011 at 11:05 PM, Song Liu<[email protected]> wrote:
Hi all,
I am trying to run flexus_test_app with 4 x86 in-order processor cores.
Besides changing "test_app_threads" and "num_cpus" to 4, I also
changed user-postload.simics:
-L2:cores = 8,
-net-mapper:Cores = 4,
-net-mapper:Directories = 4,
-network:nodes = 12,
-network:topology-file = 4x3-torus.topology,
Now I get error
<ExecuteImpl.cpp:666> {4877}- Invalid fill type: eCoherence
Any suggestion on this error?
Thanks in advance,
Song
