Hi Kim,
One other approach you might take is to change the wiring file to
replace the cache with the MemoryLoopback component and set the delay to
mimic the cache delay. This approach models something slightly better
than a "perfect" cache because it doesn't suffer any cold misses,
something that simple caching can't achieve.
If you're happy to ignore cold misses, this approach will speed up your
simulations more than using a very large cache.
Another alternative is to simply change the data array within the cache.
It should be "relatively" easy to implement an "infinite" cache
structure that will be more space and time efficient than simply
increasing the size of the existing cache structures.
Jason
On 07/04/2011 7:53 PM, Alisafaee Mohammad wrote:
Dear Kim,
There is not a perfect cache model for data caches. One thing that you can do
to simulate a perfect cache is to set cache parameter into their extreme values
(minimum values for delays and large values for size, associativity, ...). Keep
in mind that even in this case data still passes through network, L2, and
memory.
For instruction cache (uFetch) there is a "PerfectICache" parameter which
simulates a cache with infinite capacity. You still need to increase values of max cache
lines and instructions fetched per cycle to eliminate any limitation. Look into
components/uFetch/uFetchImpl.cpp for more details.
Regards,
Mohammad
On 7 Apr 2011, at 17:03, Eun-Sung Kim wrote:
Hi,
I am going to timing-simulate with perfect cache hit ratio.
How and where can I set up parameters for that?
I am using v9 target.
Thanks.
--Kim
