Dear Cansu, Thanks a lot for this information.
I looked into these two files and seems they do implement a two-level TLB. However, I didn't find any references to the functions declared in sparcmmu.hpp (mmu_lookup, etc) out of these two files. Seems that the address translation was always finished by simics. Is this true? Thanks, Song On Fri, Jun 17, 2011 at 6:47 PM, Cansu Kaynak <[email protected]> wrote: > Dear Song, > UltraSPARC 3 processors invoke software to handle TLB misses. > In FLEXUS, you can find the code that emulates the TLB hardware, which > stores the translation entries inserted by the software TLB handler > in Translation Table Entries (TTE) & Translation Storage Buffer (TSB), > under core/simics in sparcmmu.hpp and sparcmmu.cpp. > > Regards, > Cansu > > > On Jun 14, 2011, at 6:30 AM, Song Liu wrote: > > Hi, > > I am trying to simulate the performance of TLB miss. Basically, I want > to invalidate the TLB and force a TLB reload. However, I don't find > where the TLB is modeled. Could you please give me some suggestion on > it? > > My work is based on the CMP.L2SharedNUCA.OoO simulator, on Solaris 10 > system. > > Thanks, > > Song > >
