Hi, I am reading code of uArch component. There are some structure names not clear to me. Can somebody briefly explain them to me? Thanks.
SB should be store buffer, SRB should be speculative retirement buffer. But what is TSOB and SSB? In addition, there is memory queue -- theMemQueue. What does it keep? It seems that it is related to LSQ, SB and SBNAW(store buffer non-allocating-write??), because there is an assertion DBG_Assert( theLSQCount + theSBCount + theSBNAWCount == static_cast<long>(theMemQueue.size()) ); What are their relations? Thanks.
