Dear Jintang Wang,

Due to several reasons, e.g., an unsupported instruction, the Flexus results 
might not match those of the golden model (i.e., Simics). In such cases, you 
see a ‘Failed Validation’. 

Please ignore this message!

Regards,
Pejman
________________________________________
From: Wangjintang [[email protected]]
Sent: Saturday, September 14, 2013 10:42 AM
To: Lotfi Kamran Pejman; [email protected]
Subject: RE: error about run data analysis/4cpu timing_v9 model

Dear Pejman,

        Thank your reply. Using your config parameter, error disppear.

    But another error happen as the topic " Failed Validation in 
<cycle.cpp:1166> " said. There are many "failed validation" happen.



144 <microArch.cpp:403> {10000}- Timestamp: 2013-Sep-14 19:17:07
l145 <cycle.cpp:1147> {10895}- #2739[02] @v:ffffffff78863690 |93d03012| tne 
%xcc, %g0, 18              {raised Trap_Instruction_18(274)}        {squashed} 
DANGER:  Core predicted exception: 112 but simics says no exception
146 <SemanticInstruction.cpp:202> {11086}- #2759[02] @v:001002240 |86102100| 
disassembly unavailable            {retired} PostValidation failed: NPC 
mismatch flexus=v:001002244 simics=v:ffffffff78863698
147 <cycle.cpp:1166> {11086}- Failed Validation
#2759[02] @v:001002240 |86102100| disassembly unavailable               
{retired}
        OperandMap:
           rd = r-Registers[3]
           pd = r-Registers[281]
           ppd = r-Registers[11]
           operand1 = 0
           operand2 = 256
           result = 256
        DispatchEffects:
Satisfy Dependance EffectSatisfy Dependance EffectMapDestination rd, store 
mapping in pd        AnnulmentEffects:
Satisfy Dependance EffectSquash Dependance Effect       ReinstatementEffects:
Squash Dependance EffectSatisfy Dependance Effect       SquashEffects:
RestoreMapping rd to ppdFreeMapping pd  RetirementEffects:
FreeMapping ppd
148 <cycle.cpp:1147> {13737}- #4201[03] @v:ffffffff788681d0 |93d03012| tne 
%xcc, %g0, 18              {raised Trap_Instruction_18(274)}         {squashed} 
DANGER:  Core predicted exception: 112 but simics says no exception
149 <SemanticInstruction.cpp:202> {13767}- #4213[03] @v:001002240 |86102100| 
disassembly unavailable            {retired} PostValidation failed: NPC 
mismatch flexus=v:001002244 simics=v:ffffffff788681d8
150 <cycle.cpp:1166> {13767}- Failed Validation
#4213[03] @v:001002240 |86102100| disassembly unavailable               
{retired}
        OperandMap:
           rd = r-Registers[3]
           pd = r-Registers[165]
           ppd = r-Registers[11]
           operand1 = 0
           operand2 = 256
           result = 256
        DispatchEffects:
Satisfy Dependance EffectSatisfy Dependance EffectMapDestination rd, store 
mapping in pd        AnnulmentEffects:
Satisfy Dependance EffectSquash Dependance Effect       ReinstatementEffects:
Squash Dependance EffectSatisfy Dependance Effect       SquashEffects:
RestoreMapping rd to ppdFreeMapping pd  RetirementEffects:
FreeMapping ppd

Best Regards,
Jed / jintang wang



Huawei Technologies Co., Ltd.
Email: [email protected]
No.701, Jianghui RD, Binjiang District,Hangzhou 310000, P.R.China
http://www.huawei.com

-----Original Message-----
From: Lotfi Kamran Pejman [mailto:[email protected]]
Sent: Friday, September 13, 2013 6:53 PM
To: Wangjintang; [email protected]
Subject: RE: error about run data analysis/4cpu timing_v9 model

Dear Jintang Wang,

Many of the parameters in the configuration file have values that are specific 
to a uni-processor and not a processor with 4 cores. Specifically, you need to 
change the following parameters to the values specified in front of them.

flexus.set "-L2:banks"                               "4"
flexus.set "-L2:cores"                                "8"
flexus.set "-memory-map:nodes"               "4"
flexus.set "-net-mapper:MemControllers"   "4"
flexus.set "-net-mapper:MemLocation"       "0,1,2,3"

Regards,
Pejman

________________________________________
From: Wangjintang [[email protected]]
Sent: Friday, September 13, 2013 4:37 AM
To: [email protected]
Subject: error about run data analysis/4cpu timing_v9 model

Hi,

run data analysis/4cpu timing_v9 model, using the "run_job -ma -cfg timing_v9 
-run timing -local UP.OoO classification/4cpu",
there is something wrong as below, I think maybe some configuration parameter 
wrong.
Could you give some suggestions? Hopy your reply.

The attach files are configure and debug file.


WARNING: switch 3 port 6 left unused (may be safe)
128 <ComponentManager.cpp:98> {0}- Initalizing sys-memory-map
129 <MemoryMapImpl.cpp:326> {0}- Page map file page_map.out was not found.
130 <ComponentManager.cpp:98> {0}- Initalizing sys-magic-break
131 <ComponentManager.cpp:98> {0}- Initalizing sys-net-mapper
132 <SplitDestinationMapperImpl.cpp:139> {0}- sys-net-mapper Creating 
SplitDestinationMapper with 4 cores, 4 directories, and 1 memory controllers.
133 <WhiteBoxImpl.cpp:172> {190}- initializing idle_thread_t's, num procs=4  
sys width=4
134 <WhiteBoxImpl.cpp:189> {190}- CPU[0] idle_thread_t point at paddr: 
p:000000000
135 <WhiteBoxImpl.cpp:197> {190}- No CPU was able to translate the virtual 
address of the cpu struct for cpu 1
136 <mai_api.cpp:96> {190}- CPU[0] Registering for interrupts
simics-common: 
/home/Flexus/boost_1_33_1/boost/dynamic_bitset/dynamic_bitset.hpp:934: bool 
boost::dynamic_bitset<Block, Allocator>::test(size_t) const [with Block = long 
unsigned int, Allocator = std::allocator<long unsigned int>]: Assertion `pos < 
m_num_bits' failed.
Abort (SIGABRT) in main thread
Crash stack trace:
#0 0x00007f552612cb55 <unknown>
#1 0x616e79643a3a7473 <unknown>
./go.sh: line 4: 111812 Segmentation fault      
/opt/virtutech/simics-3.0.31/scripts/start-simics -no-copyright -x start.simics 
-no-win -ma -batch-mode -q
Cannot open stats database ../stats_db.out.gz

Best Regards,
Jed / jintang wang

Huawei Technologies Co., Ltd.
Email: [email protected]
No.701, Jianghui RD, Binjiang District,Hangzhou 310000, P.R.China
http://www.huawei.com

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