Hello Jagadish, The problem probably lies in the following line of your configuration: flexus.set "-L2:cores" "4"
This parameter indicates how many L1 caches the L2 cache is attached to, which is 2x number of cores (one instruction and one data cache per core). In your case it should be set to 8. Regards, Djordje ________________________________________ From: [email protected] [[email protected]] on behalf of Jagadish Kotra [[email protected]] Sent: Tuesday, July 29, 2014 9:51 PM To: [email protected] Subject: CMP.L2SharedNUCA.OoO Assertion Failed Error Hello, I get the following error when I am trying to run a timing simulation with 4 core CMP .. 72 <WhiteBoxImpl.cpp:172> {4}- initializing idle_thread_t's, num procs=1 sys width=1 72 <WhiteBoxImpl.cpp:172> {4}- initializing idle_thread_t's, num procs=1 sys width=1 73 <WhiteBoxImpl.cpp:189> {4}- CPU[0] idle_thread_t point at paddr: p:000000000 73 <WhiteBoxImpl.cpp:189> {4}- CPU[0] idle_thread_t point at paddr: p:000000000 74 <mai_api.cpp:96> {4}- CPU[0] Registering for interrupts 74 <mai_api.cpp:96> {4}- CPU[0] Registering for interrupts 75 <component.hpp:274> {44}- <undefined> Assertion failed: ((!(anIndex < theWidth))) : Component: nic Index: 4 Width: 3 I am currently using a 4x3-mesh.topology. Please find my configuration.out file attached to this email. Can you please let me know what am I doing wrong here! Regards, Jagadish.
