Dear Huijuan, Please send your questions to the mailing list - others may benefit from them.
You can implement models with the level of detail you desire. The implementation difficulty depends on the complexity of the component you want to model and its interactions with other components. Related to your question, in order to simulate NUMA you have to instantiate multiple MemoryLoopback (or DRAMController) components and give them asymmetric latencies. Since you are not very familiar with the simulator, I would suggest that you study the existing models in the Flexus distribution to see which of them you can use them as is or as a basis for implementing the models of other components. Regards, Georgios From: 百灵鸟<mailto:[email protected]> Sent: Thursday, February 12, 2015 10:54 AM To: Georgios Psaropoulos<mailto:[email protected]> Dear Georgios Thanks for your response. Does this mean I have to implement all related models about NUMA or just some models I use to get particular values? I am just starting with flexus and still not familiar with this tool. Are these models easy to be implemented? Thanks for your help. Best, Huijuan ------------------ 原始邮件 ------------------ 发件人: "Psaropoulos Georgios";<[email protected]>; 发送时间: 2015年2月11日(星期三) 晚上8:37 收件人: "[email protected]"<[email protected]>; 主题: Re: Some doubts about the simulation of NUMA Dear Huijuan, Flexus is capable of simulating models of the hardware components you mention, but it is not in its scope to provide them out-of-the-box - the user has to implement models for the components they are interested in. Regards, Georgios From: 百灵鸟 [[email protected]] Sent: Friday, February 06, 2015 12:50 PM To: simflex Subject: Some doubts about the simulation of NUMA Dear Mr/Miss, I have some doubts about the simulation of the NUMA micro-architecture using flexus. Can flexus simulate the micro-architecture of NUMA? I saw many material about the micro-architecture of SMP, but few about NUMA. Does flexus support detailed UNCORE configuration of the Westmere-EP（Intel micro-architecture ）,e.g. GQ (global queue) event,QHL (QPI home logic)? And is the QPI a link pair,not a bus? Looking forward to your letter. Thanks. Have a nice day! Sincerely, Huijuan Li
