Hello, I am trying to use Flexus 4.1 to simulate DRAM
(CMP.L2SharedNUCA.DRAMSim.OoO). I am interested in simulating rowbuffer
hit/miss rate, so I added code in MemoryController::update() to log each
DRAM command (precharge, activate, read, write, and refresh). I
consider a "hit" to be two activate commands to the same rank, bank, and
row, and a "miss" to be an activate command sent to a different row from
the last activate command sent to the same rank and bank.
Could someone let me know if this reasonable, to presume the behavior of
the simulated rowbuffer from the sequence of commands processed in
MemoryController.cpp? I'm not sure, the hit/miss rates from running
Cloudsuite are not what I was expecting.
Thank you,
-Mark Meredith
