Hi Stephen,
Thanks for the help last time :)
I am facing some fresh problems with CMPFlex. Several applications give
assertion failure during timing simulations using CMPFlex. The checkpoints
for the same have been generated correctly using TraceCMPFlex. However, when
I use the run-timing-job script on these checkpoints, some of the them give
a 'l2lookup.hit()' assertion failure in the PiranhaCacheController, while
some give segmentation fault. Before going into the source code of CMPFlex
simulator, I am just wondering whether I am making some other mistake. Note
that I have also set the configurations L2:offchip_stream_fetch and
L2:allow_bypass_bus' since I am using the inorder simulations only.
Heres the sample output for CMPFlex for the first checkpoints
(flexpoint_000):
----------------------------------------------
Flexus Simics simulator - Built as CMPFlex v3.0
2 <ComponentManager.cpp:81> {0}- Instantiating system with a width factor
of: 8
3 <InorderSimicsFeederImpl.cpp:284> (feeder[<undefined>]) {0}- Initializing
InorderSimicsFeeder.
4 <InorderSimicsFeederImpl.cpp:332> (feeder[<undefined>]) {0}- Connecting:
cpu0
5 <InorderSimicsFeederImpl.cpp:332> (feeder[<undefined>]) {0}- Connecting:
cpu1
6 <InorderSimicsFeederImpl.cpp:332> (feeder[<undefined>]) {0}- Connecting:
cpu2
7 <InorderSimicsFeederImpl.cpp:332> (feeder[<undefined>]) {0}- Connecting:
cpu3
8 <InorderSimicsFeederImpl.cpp:332> (feeder[<undefined>]) {0}- Connecting:
cpu4
9 <InorderSimicsFeederImpl.cpp:332> (feeder[<undefined>]) {0}- Connecting:
cpu5
10 <InorderSimicsFeederImpl.cpp:332> (feeder[<undefined>]) {0}- Connecting:
cpu6
11 <InorderSimicsFeederImpl.cpp:332> (feeder[<undefined>]) {0}- Connecting:
cpu7
[cpu0 info] Note that on this cpu, instruction-fetch-trace is implemented
using instruction-cache-access-trace with a suitable cache line size.
[cpu1 info] Note that on this cpu, instruction-fetch-trace is implemented
using instruction-cache-access-trace with a suitable cache line size.
[cpu2 info] Note that on this cpu, instruction-fetch-trace is implemented
using instruction-cache-access-trace with a suitable cache line size.
[cpu3 info] Note that on this cpu, instruction-fetch-trace is implemented
using instruction-cache-access-trace with a suitable cache line size.
[cpu4 info] Note that on this cpu, instruction-fetch-trace is implemented
using instruction-cache-access-trace with a suitable cache line size.
[cpu5 info] Note that on this cpu, instruction-fetch-trace is implemented
using instruction-cache-access-trace with a suitable cache line size.
[cpu6 info] Note that on this cpu, instruction-fetch-trace is implemented
using instruction-cache-access-trace with a suitable cache line size.
[cpu7 info] Note that on this cpu, instruction-fetch-trace is implemented
using instruction-cache-access-trace with a suitable cache line size.
12 <Cache.hpp:82> {0}- L1d port BackSideOut_Prefetch is not wired
13 <Cache.hpp:82> {0}- L1d port BackSideOut_Prefetch is not wired
14 <Cache.hpp:82> {0}- L1d port BackSideOut_Prefetch is not wired
15 <Cache.hpp:82> {0}- L1d port BackSideOut_Prefetch is not wired
16 <Cache.hpp:82> {0}- L1d port BackSideOut_Prefetch is not wired
17 <Cache.hpp:82> {0}- L1d port BackSideOut_Prefetch is not wired
18 <Cache.hpp:82> {0}- L1d port BackSideOut_Prefetch is not wired
19 <Cache.hpp:82> {0}- L1d port BackSideOut_Prefetch is not wired
20 <Cache.hpp:82> {0}- L1i port BackSideOut_Prefetch is not wired
21 <Cache.hpp:82> {0}- L1i port BackSideOut_Prefetch is not wired
22 <Cache.hpp:82> {0}- L1i port BackSideOut_Prefetch is not wired
23 <Cache.hpp:82> {0}- L1i port BackSideOut_Prefetch is not wired
24 <Cache.hpp:82> {0}- L1i port BackSideOut_Prefetch is not wired
25 <Cache.hpp:82> {0}- L1i port BackSideOut_Prefetch is not wired
26 <Cache.hpp:82> {0}- L1i port BackSideOut_Prefetch is not wired
27 <Cache.hpp:82> {0}- L1i port BackSideOut_Prefetch is not wired
28 <CmpCache.hpp:90> {0}- L2 port BackSideOut_Snoop is not wired
29 <CmpCache.hpp:90> {0}- L2 port BackSideOut_Prefetch is not wired
30 <wiring.cpp:88> {0}- initializing Parameters...
Warning: The 'flexus-CMPFlex-v9-iface-gcc' module unexpectedly defined the
'Flexus' class
Warning: The 'flexus-CMPFlex-v9-iface-gcc' module unexpectedly defined the
'SimicsInterface' class
Warning: The 'flexus-CMPFlex-v9-iface-gcc' module unexpectedly defined the
'InOrderFeeder' class
31 <flexus.cpp:377> {0}- Set stat interval to : 50000
32 <flexus.cpp:382> {0}- Set region interval to : 50000
Opening debug output file: trace.out
Successfully parsed debug configurations from iteration.trace.cfg
33 <flexus.cpp:521> {0}- Loading Flexus state from subdirectory
flex_state_in
34 <ComponentManager.cpp:96> {0}- Initalizing components...
35 <InorderSimicsFeederImpl.cpp:271> (feeder[<undefined>]) {0}- Using new
scheduling mechanism.
36 <IFetchImpl.cpp:100> {0}- StallInstructions: 1
37 <IFetchImpl.cpp:100> {0}- StallInstructions: 1
38 <IFetchImpl.cpp:100> {0}- StallInstructions: 1
39 <IFetchImpl.cpp:100> {0}- StallInstructions: 1
40 <IFetchImpl.cpp:100> {0}- StallInstructions: 1
41 <IFetchImpl.cpp:100> {0}- StallInstructions: 1
42 <IFetchImpl.cpp:100> {0}- StallInstructions: 1
43 <IFetchImpl.cpp:100> {0}- StallInstructions: 1
44 <ExecuteImpl.cpp:309> {0}- EX initalized
45 <ExecuteImpl.cpp:312> {0}- Sequential Consistency Enabled
46 <ExecuteImpl.cpp:309> {0}- EX initalized
47 <ExecuteImpl.cpp:312> {0}- Sequential Consistency Enabled
48 <ExecuteImpl.cpp:309> {0}- EX initalized
49 <ExecuteImpl.cpp:312> {0}- Sequential Consistency Enabled
50 <ExecuteImpl.cpp:309> {0}- EX initalized
51 <ExecuteImpl.cpp:312> {0}- Sequential Consistency Enabled
52 <ExecuteImpl.cpp:309> {0}- EX initalized
53 <ExecuteImpl.cpp:312> {0}- Sequential Consistency Enabled
54 <ExecuteImpl.cpp:309> {0}- EX initalized
55 <ExecuteImpl.cpp:312> {0}- Sequential Consistency Enabled
56 <ExecuteImpl.cpp:309> {0}- EX initalized
57 <ExecuteImpl.cpp:312> {0}- Sequential Consistency Enabled
58 <ExecuteImpl.cpp:309> {0}- EX initalized
59 <ExecuteImpl.cpp:312> {0}- Sequential Consistency Enabled
60 <MemoryMapImpl.cpp:322> {0}- Page map file page_map.out was not found.
61 <ComponentManager.cpp:127> {0}- Loading state: sys-feeder
62 <ComponentManager.cpp:127> {0}- Loading state: 00-L1d
63 <ComponentManager.cpp:127> {0}- Loading state: 01-L1d
64 <ComponentManager.cpp:127> {0}- Loading state: 02-L1d
65 <ComponentManager.cpp:127> {0}- Loading state: 03-L1d
66 <ComponentManager.cpp:127> {0}- Loading state: 04-L1d
67 <ComponentManager.cpp:127> {0}- Loading state: 05-L1d
68 <ComponentManager.cpp:127> {0}- Loading state: 06-L1d
69 <ComponentManager.cpp:127> {0}- Loading state: 07-L1d
70 <ComponentManager.cpp:127> {0}- Loading state: 00-L1i
71 <ComponentManager.cpp:127> {0}- Loading state: 01-L1i
72 <ComponentManager.cpp:127> {0}- Loading state: 02-L1i
73 <ComponentManager.cpp:127> {0}- Loading state: 03-L1i
74 <ComponentManager.cpp:127> {0}- Loading state: 04-L1i
75 <ComponentManager.cpp:127> {0}- Loading state: 05-L1i
76 <ComponentManager.cpp:127> {0}- Loading state: 06-L1i
77 <ComponentManager.cpp:127> {0}- Loading state: 07-L1i
78 <ComponentManager.cpp:127> {0}- Loading state: 00-fetch
79 <ComponentManager.cpp:127> {0}- Loading state: 01-fetch
80 <ComponentManager.cpp:127> {0}- Loading state: 02-fetch
81 <ComponentManager.cpp:127> {0}- Loading state: 03-fetch
82 <ComponentManager.cpp:127> {0}- Loading state: 04-fetch
83 <ComponentManager.cpp:127> {0}- Loading state: 05-fetch
84 <ComponentManager.cpp:127> {0}- Loading state: 06-fetch
85 <ComponentManager.cpp:127> {0}- Loading state: 07-fetch
86 <ComponentManager.cpp:127> {0}- Loading state: 00-execute
87 <ComponentManager.cpp:127> {0}- Loading state: 01-execute
88 <ComponentManager.cpp:127> {0}- Loading state: 02-execute
89 <ComponentManager.cpp:127> {0}- Loading state: 03-execute
90 <ComponentManager.cpp:127> {0}- Loading state: 04-execute
91 <ComponentManager.cpp:127> {0}- Loading state: 05-execute
92 <ComponentManager.cpp:127> {0}- Loading state: 06-execute
93 <ComponentManager.cpp:127> {0}- Loading state: 07-execute
94 <ComponentManager.cpp:127> {0}- Loading state: 00-bpwarm
95 <BranchPredictor.cpp:1090> {0}- 00-bpwarm loaded branch predictor. BTB
size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
96 <ComponentManager.cpp:127> {0}- Loading state: 01-bpwarm
97 <BranchPredictor.cpp:1090> {0}- 01-bpwarm loaded branch predictor. BTB
size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
98 <ComponentManager.cpp:127> {0}- Loading state: 02-bpwarm
99 <BranchPredictor.cpp:1090> {0}- 02-bpwarm loaded branch predictor. BTB
size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
100 <ComponentManager.cpp:127> {0}- Loading state: 03-bpwarm
101 <BranchPredictor.cpp:1090> {0}- 03-bpwarm loaded branch predictor. BTB
size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
102 <ComponentManager.cpp:127> {0}- Loading state: 04-bpwarm
103 <BranchPredictor.cpp:1090> {0}- 04-bpwarm loaded branch predictor. BTB
size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
104 <ComponentManager.cpp:127> {0}- Loading state: 05-bpwarm
105 <BranchPredictor.cpp:1090> {0}- 05-bpwarm loaded branch predictor. BTB
size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
106 <ComponentManager.cpp:127> {0}- Loading state: 06-bpwarm
107 <BranchPredictor.cpp:1090> {0}- 06-bpwarm loaded branch predictor. BTB
size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
108 <ComponentManager.cpp:127> {0}- Loading state: 07-bpwarm
109 <BranchPredictor.cpp:1090> {0}- 07-bpwarm loaded branch predictor. BTB
size: 1024 by 16 Bimodal size: 32768 Meta size: 8192 Gshare size: 13
110 <ComponentManager.cpp:127> {0}- Loading state: sys-L2
111 <ComponentManager.cpp:127> {0}- Loading state: sys-memory
112 <ComponentManager.cpp:127> {0}- Loading state: sys-memory-map
113 <MemoryMapImpl.cpp:322> {0}- Page map file page_map.out was not found.
114 <ComponentManager.cpp:127> {0}- Loading state: sys-magic-break
115 <ComponentManager.cpp:131> {0}- Done loading.
116 <PiranhaCacheControllerImpl.cpp:561> (<undefined>[<undefined>]) {13244}-
Assertion failed: ((!(l2Lookup.hit()))) : Failed: PDEntry: 0x300c200 dir
state: PiranhaDirState[D_M] #sharers: 0 sharersList: 0 Owner: -1 acount: 0
MemoryMessage[Read Request]: Addr:0xp:80300c200 Size:64 Serial: 31040 Core:
1
Abort (SIGABRT) in main thread
The simulation state has been corrupted. Simulation cannot continue.
Please restart Simics.
----------------------------------------------
Please let me know.
Thanks,
Abhishek
On Thu, May 21, 2009 at 2:59 PM, Stephen Somogyi <ssomogyi at ece.cmu.edu>wrote:
> Dear Abhishek,
>
> I apologize for my tardy response (I had been travelling and your message
> fell by the wayside).
>
> I did not realize you were relying on the CMP cache. As you have noticed,
> unfortunately the FastCMPCache has not been instrumented with TraceTracker
> callbacks. A couple options:
> - add TraceTracker callbacks to the FastCMPCache
> - look at the fillLevel as observed at the L1 cache
> - see theTraceTracker.fill() calls for examples
> - eLocalMem or eRemoteMem indicate that the request went off-chip
> - ePeerL1Cache indicates the data came from another core's L1 cache
> - eL2 indicates the L2 cache had an up-to-date value for the block
>
> Thus, by looking at the fillLevel, you can examine the exact subset of
> memory accesses that you care about (e.g., only to main memory, only
> filled on chip, etc).
>
> To answer your other question, if the wiring.cpp file for a particular
> simulator does not initialize a parameter that you know to exist, you can
> simply add it (to initializeParameters() in wiring.cpp). Or just set the
> parameter as you need after Flexus has been loaded (look at the
> configuration.simics files for examples).
>
> Regards,
> Stephen
>
>
> On Thu, 7 May 2009, Abhishek Das wrote:
>
> > Hi Stephen,
> >
> > The 'TraceTracker.initialize()' call only works for the FastCache
> component
> > of the TraceFlex(TraceCMPFlex) simulator. However, the FastCMPCache
> > component doesn't allow you to load the TraceTracker component. Hence the
> L2
> > accesses cannot be traced. Also, for CMPFlex/UniFlex type of simulators,
> > neither of Cache or CMPCache component has TraceTracking options. How do
> I
> > enable tracking for L2 cache under such circumstances? Is there a way
> > around?
> >
> > Thanks,
> > Abhishek
> >
> > -----Original Message-----
> > From: simflex-bounces at ece.cmu.edu [mailto:simflex-bounces at ece.cmu.edu]
> On
> > Behalf Of Stephen Somogyi
> > Sent: Thursday, April 30, 2009 10:17 AM
> > To: SimFlex software support
> > Subject: Re: [Simflex] memory access traces
> >
> > Hi Abhishek,
> >
> > Actually, the TraceTracker works a bit strangely compared with most of
> the
> > other Flexus components. You can get callbacks into TraceTracker even if
> > the TraceTrackerComponent is not enabled (basically, the code in
> > components/Common/TraceTracker.* is always active, even if the component
> > in components/TraceTracker/ is not).
> >
> > If you are using TraceFlex (or one of its variants), you will need to
> > enable the callbacks from within the caches, for example:
> > - at run-time: flexus.set "-L1d:trace_tracker_on" "1"
> > - at compile time (in wiring.cpp, initializeParameters() function:
> > theL1DCfg.TraceTracker.initialize(true);
> >
> > The easiest way to get a list of all the parameters supported by a
> > particular Flexus simulator is to load the simulator in Simics and run,
> > even if just for one cycle. Then look at the configuration.out file that
> > was generated - this lists all the parameters and their values.
> >
> > Stephen
> >
> >
> > On Wed, 29 Apr 2009, Abhishek Das wrote:
> >
> > > Hi Stephen,
> > >
> > > Thanks for the reply. I have put my own debugging statements in the
> > > components/Common/TraceTracker.cpp file. However, it seems that I need
> to
> > > enable the trace-tracking option in order to get the extra information.
> > The
> > > components/TraceTrackerComponent.hpp has a parameter called "enable"
> which
> > > is set to 'false' by default. How can I enable this option? Should I
> > include
> > > the command { flexus.set "trace-tracker:enable" "true" } in the
> > > config/flexpoint/start.simics ?
> > >
> > > Also, in general where can I get the complete list of component names
> and
> > > corresponding parameters which can be used for the 'flexus.set'
> > statements.
> > > Currently, I am just looking at the *.hpp files in the components
> > directory,
> > > but I am unsure of the names of the components to use.
> > >
> > > regards,
> > > Abhishek
> > >
> > > -----Original Message-----
> > > From: simflex-bounces at ece.cmu.edu [mailto:simflex-bounces at
> > > ece.cmu.edu]
> On
> > > Behalf Of Stephen Somogyi
> > > Sent: Tuesday, April 28, 2009 11:05 AM
> > > To: SimFlex software support
> > > Subject: Re: [Simflex] memory access traces
> > >
> > > Dear Abhishek,
> > >
> > > Probably the easiest way to accomplish this in Flexus is through the
> > > TraceTracker. Each cache makes a call into TraceTracker on every
> access,
> > > which should provide the information you require. The default
> > > TraceTracker functions perform no actions, but it is simple to add
> > > whatever code you need (components/Common/TraceTracker.cpp). To get
> the
> > > current cycle, call "theFlexus->cycleCount()".
> > >
> > > Cheers,
> > > Stephen
> > >
> > >
> > > On Mon, 27 Apr 2009, Abhishek Das wrote:
> > >
> > > > Hi,
> > > >
> > > >
> > > >
> > > > I am trying to generate memory traces for some applications using
> > Flexus.
> > > > Particularly, I want to track memory accesses by each thread/cpu
> (read,
> > > > write, load, store) to physical addresses in memory. I want an output
> > > > registers the follwwing information:
> > > >
> > > > Cpu/Thread Memory Request Physical Addres
> > > > Cycle
> > > >
> > > > --------------- ----------------------
> > > --------------------
> > > > ----------
> > > >
> > > >
> > > >
> > > > I was wondering whether Simflex has debugging options that can enable
> > such
> > > > memory access tracing. If yes, what specific debug flags need to be
> set?
> > > Or
> > > > do I have to change in the source code in Flexus to do the same?
> > > >
> > > >
> > > >
> > > > Thanks,
> > > >
> > > > Abhishek
> > > >
> > > >
> > > _______________________________________________
> > > SimFlex mailing list
> > > SimFlex at ece.cmu.edu
> > > https://sos.ece.cmu.edu/mailman/listinfo/simflex
> > > SimFlex web page:
> > > http://www.ece.cmu.edu/~simflex<http://www.ece.cmu.edu/%7Esimflex>
> > >
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> > > SimFlex mailing list
> > > SimFlex at ece.cmu.edu
> > > https://sos.ece.cmu.edu/mailman/listinfo/simflex
> > > SimFlex web page:
> > > http://www.ece.cmu.edu/~simflex<http://www.ece.cmu.edu/%7Esimflex>
> > >
> > _______________________________________________
> > SimFlex mailing list
> > SimFlex at ece.cmu.edu
> > https://sos.ece.cmu.edu/mailman/listinfo/simflex
> > SimFlex web page:
> > http://www.ece.cmu.edu/~simflex<http://www.ece.cmu.edu/%7Esimflex>
> >
> > _______________________________________________
> > SimFlex mailing list
> > SimFlex at ece.cmu.edu
> > https://sos.ece.cmu.edu/mailman/listinfo/simflex
> > SimFlex web page:
> > http://www.ece.cmu.edu/~simflex<http://www.ece.cmu.edu/%7Esimflex>
> >
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