Hi Lu,
On Sat, 29 Apr 2006, lu peng wrote:
>
> Hi Tom,
>
> Thanks for your quick reply. Actually I am trying to implement a 2-level
> cache with private inclusive L1 and L2. I just saw your post of implementing
> an inclusive cache by adding a messge and bit. That's good. To make L2
> private, what kind of simple snooping component should I add? Any existing
> examples in the source code?
>
An off chip interface component for a private caches in a CMP has to
perform 3 functions:
1) Multiplex/route responses to the correct L2 cache. When an L2 issues
a miss, it needs to get the miss reply. Take a look at the IDCacheMux
or CmpCache components to see ways to do this.
2) Perform snoopy coherence between the L2's. Everytime you receive a
write request from one of the L2's, you need to send an Invalidate to
the others (and wait for the reply, which may contain data).
Every time you receive a Read request, you must send Downgrade to all
the others. If you want, you could implement a directory/duplicate
tag array that optimizes away unneccessary Invalidates/Downgrades, but
this is not neccessary for correctness. You can look at the FastBus
for some ideas on how to implement this.
3) If you intend to hook multiple chips into a larger multiprocessor
(i.e., DSM or SMP of CMPs), then you also need to send any external
coherence traffic (invalidates and downgrades) to all L2s, and then
wait for their replies.
Regards,
-Tom Wenisch
Computer Architecture Lab
Carnegie Mellon University
