There probably is a way to verify the fetch-mode from within Flexus. However, instruction fetching slows simulation by up to 3x in our experience. For flexpoint creation (or anything else that looks at the I-cache), you obviously need to enable this setting. Conversely, for research that only looks at data accesses, it is generally preferable to take advantage of the simulation speedup by leaving instruction fetch off.
Stephen On Tue, 7 Nov 2006, Jason Zebchuk wrote: > Thanks Stephen. > > Is there anyway to check for this setting from inside flexus? > > It would be really nice if TraceFlex complained if this setting wasn't set. > > > Jason > > > > Stephen Somogyi wrote: > > >Due to issues with Simics, we cannot reliably turn on instruction tracing > >through Flexus. Instead, you must directly tell Simics to enable > >instruction tracing with the following command (at the Simics prompt): > > instruction-fetch-mode instruction-fetch-trace > > > >Cheers, > >Stephen > > > > > >On Tue, 7 Nov 2006, Jason Zebchuk wrote: > > > > > > > >>Hi guys, > >> > >>When running TraceFlex and TraceCMPFlex, it looks like the L1I cache and > >>the branch predictor are not working at all. > >> > >>After running for a couple million instructions, I do > >>"flexus.print-measurement all" and all the stats for L1i and for bpwarm > >>are 0. The other stats have non-zero values but it looks like the > >>icache and branch predictor just aren't being used. > >> > >>Also, looking at the flexus state that gets saved in the flexpoints, the > >>bpred files seem to have practically no information in them. Viewing > >>them with 'od -x' shows that most of the file is zeroes. > >> > >>Any thoughts on what might be going on? I have included my > >>configuration below. > >> > >> > >>Thanks, > >> > >>Jason > >> > >> > >>-L1d:assoc 4 # (Associativity) Set > >>associativity > >>-L1d:bsize 64 # (BlockSize) Block size > >>-L1d:clean_evict 0 # (CleanEvictions) > >>Issue clean evictions > >>-L1d:level 1 # (CacheLevel) CacheLevel > >>-L1d:mt_width 1 # (MTWidth) Number of > >>threads sharing this cache > >>-L1d:notify_reads 0 # (NotifyReads) > >>Notify on reads (does not notify on fast-hit) > >>-L1d:notify_writes 0 # (NotifyWrites) > >>Notify on writes > >>-L1d:size 32768 # (Size) Cache size > >>in bytes > >>-L1d:trace_tracker_on 0 # (TraceTracker) Turn > >>trace tracker on/off > >>-L1i:assoc 4 # (Associativity) Set > >>associativity > >>-L1i:bsize 64 # (BlockSize) Block size > >>-L1i:clean_evict 0 # (CleanEvictions) > >>Issue clean evictions > >>-L1i:level 9 # (CacheLevel) CacheLevel > >>-L1i:mt_width 1 # (MTWidth) Number of > >>threads sharing this cache > >>-L1i:notify_reads 0 # (NotifyReads) > >>Notify on reads (does not notify on fast-hit) > >>-L1i:notify_writes 0 # (NotifyWrites) > >>Notify on writes > >>-L1i:size 32768 # (Size) Cache size > >>in bytes > >>-L1i:trace_tracker_on 0 # (TraceTracker) Turn > >>trace tracker on/off > >>-L2:assoc 16 # (Associativity) Set > >>associativity > >>-L2:bsize 64 # (BlockSize) Block size > >>-L2:clean_evict 0 # (CleanEvictions) > >>Issue clean evictions > >>-L2:level 2 # (CacheLevel) CacheLevel > >>-L2:mt_width 1 # (MTWidth) Number of > >>threads sharing this cache > >>-L2:notify_reads 0 # (NotifyReads) > >>Notify on reads (does not notify on fast-hit) > >>-L2:notify_writes 0 # (NotifyWrites) > >>Notify on writes > >>-L2:size 8388608 # (Size) Cache size > >>in bytes > >>-L2:trace_tracker_on 0 # (TraceTracker) Turn > >>trace tracker on/off > >>-bpwarm:cores 1 # (Cores) Number of cores > >>-bus:bsize 64 # (BlockSize) Size of > >>coherence unit > >>-bus:dma 1 # (TrackDMA) Track > >>DMA blocks > >>-bus:evictions 0 # (TrackEvictions) > >>Track/Notify on evictions > >>-bus:flushes 0 # (TrackFlushes) > >>Track/Notify on flushes > >>-bus:invalall 0 # (InvalAll) > >>Invalidate all nodes on exclusive > >>-bus:invalidations 0 # > >>(TrackInvalidations) Track/Notify on invalidations > >>-bus:offchipreads 0 # (TrackReads) > >>Track/Notify on off-chip reads > >>-bus:pagesize 8192 # (PageSize) Page > >>size in bytes > >>-bus:productions 0 # (TrackProductions) > >>Track/Notify on productions > >>-bus:round_robin 1 # (RoundRobin) Use > >>static round-robin page allocation > >>-bus:save_page_map 0 # (SavePageMap) Save > >>page_map.out in checkpoints > >>-bus:upgrades 0 # (TrackWrites) > >>Track/Notify on upgrades > >>-feeder:housekeeping_period 1000 # > >>(HousekeepingPeriod) Simics cycles between housekeeping events > >>-feeder:ifetch 1 # (TrackIFetch) Track > >>and report instruction fetches > >>-feeder:simics_quantum 100 # (SimicsQuantum) CPU > >>quantum size in simics > >>-feeder:stick 0 # > >>(SystemTickFrequency) CPU System tick frequency. 0.0 leaves frequency > >>unchanged > >>-magic-break:ckpt_cycle 0 # (CkptCycleInterval) > >># of cycles between checkpoints. > >>-magic-break:ckpt_cycle_name 0 # (CkptCycleName) > >>Base cycle # from which to build checkpoint names. > >>-magic-break:ckpt_iter 0 # > >>(CheckpointOnIteration) Checkpoint simulation when CPU 0 reaches each > >>iteration. > >>-magic-break:ckpt_trans 0 # > >>(CheckpointEveryXTransactions) Quiesce and save every X transactions. -1 > >>disables > >>-magic-break:end_iter -1 # > >>(TerminateOnIteration) Terminate simulation when CPU 0 reaches > >>iteration. -1 disables > >>-magic-break:end_trans -1 # > >>(TerminateOnTransaction) Terminate simulation after ## transactions. -1 > >>disables > >>-magic-break:first_trans 0 # > >>(FirstTransactionIs) Transaction number for first transaction. > >>-magic-break:iter 0 # > >>(EnableIterationCounts) Enable Iteration Counts > >>-magic-break:min_cycle 0 # (CycleMinimum) > >>Minimum number of cycles to run when TerminateOnTransaction is enabled. > >>-magic-break:stats_trans 10000 # > >>(TransactionStatsInterval) Statistics interval on ## transactions. -1 > >>disables > >>-magic-break:stop_cycle 0 # (StopCycle) Cycle > >>on which to halt simulation. > >>-magic-break:stop_on_magic -1 # > >>(TerminateOnMagicBreak) Terminate simulation on a specific magic breakpoint > >>-magic-break:trans 0 # > >>(EnableTransactionCounts) Enable Transaction Counts > >>-magic-break:trans_type 0 # (TransactionType) > >>Workload type. 0=TPCC/JBB 1=WEB > >> > >>_______________________________________________ > >>SimFlex mailing list > >>[email protected] > >>https://sos.ece.cmu.edu/mailman/listinfo/simflex > >>SimFlex web page: http://www.ece.cmu.edu/~simflex > >> > >> > >> > >_______________________________________________ > >SimFlex mailing list > >[email protected] > >https://sos.ece.cmu.edu/mailman/listinfo/simflex > >SimFlex web page: http://www.ece.cmu.edu/~simflex > > > > > > _______________________________________________ > SimFlex mailing list > [email protected] > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: http://www.ece.cmu.edu/~simflex >
