Dear Niko, Thank you for your answer! What I meant with cache partitioning is the dynamic partitioning of the ways of a shared LLC between the processors of a CMP system using various policies/metrics. Sorry for the inconvenience. However, I have found the modules that I should modify in order to implement this algorithm, so that's ok.
One question on the "make" of the CMPFlex simulator: When I try to compile CMPFlex I get the message: /usr/include/c++/4.2/x86_64-linux-gnu/bits/c++config.h:149: error: expected constructor, destructor, or type conversion before 'namespace' Any clue on what might be the problem? I have used the gcc and simics versions proposed in the Simflex tutorial.. Thank you for your help, Christina 2009/4/15 Nikos Hardavellas <hardav at cs.cmu.edu> > Dear Christina, > > > > I assume that by ?partitioning? you mean dividing the cache into smaller > pieces and assigning each piece to a core (e.g., a NUCA cache). > > In the current SimFlex release, the cache is not partitioned among the > cores; rather, it looks like a single structure that all cores share. > > To create a NUCA cache, you need to instantiate multiple objects of the > cache (each object being a separate cache partition), connect them together > through an on-chip interconnection network using NetShim, and assign each > cache partition to a core. Care must be taken to maintain data coherence > among the partitions, avoid deadlock (i.e., have separate channels for > requests and replies to break dependency cycles) and do the routing properly > (e.g., configure NetShim with a correct network topology and do > dimensionality minimal source routing to avoid deadlocks at the network). > > > > If by ?partitioning? you mean something different, please give us more > details. > > > > Regards, > > --nikos > > > > > > *Nikos Hardavellas* > Carnegie Mellon - Computer Science Department > 5000 Forbes Ave, Pittsburgh, PA 15213, USA > +1 (412) 268-5005 ECE - Hamerschlag Hall A312 > http://www.cs.cmu.edu/~hardav <http://www.cs.cmu.edu/%7Ehardav>* > **hardavellas at cmu.edu* > > *From:* simflex-bounces at ece.cmu.edu [mailto:simflex-bounces at > ece.cmu.edu] *On > Behalf Of *Christina Delimitrou > *Sent:* Wednesday, April 08, 2009 7:36 AM > *To:* simflex at ece.cmu.edu > *Subject:* [Simflex] Cache partitioning policies using Simflex > > > > Hello, > > I am currently working on cache partitioning policies for CMP architectures > and wanted to ask if there is a way to use Simflex to achieve a faster > simulation for these schemes. I imagine that I will need to modify the > simulators' modules CMPFlex and TraceFlex to partition the shared cache > among the cores and I was wondering if I also need to change the > implementation of the components FastCache or CmpCache.. (1) Is there any > prior implementation for a cache partitioning algorithm in Simflex and (2) > was is the default cache partitioning scheme you use? > > Thank you, > Christina > > -- > Undergraduate Student > Electrical and Computer Engineering Department > National Technical University of Athens > Computer Systems Lab > +30 210 6513839, +30 6947424452 > http://users.ntua.gr/el04019/Homepage/Home.html > > _______________________________________________ > SimFlex mailing list > SimFlex at ece.cmu.edu > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: > http://www.ece.cmu.edu/~simflex<http://www.ece.cmu.edu/%7Esimflex> > > -- Undergraduate Student Electrical and Computer Engineering Department National Technical University of Athens Computer Systems Lab +30 210 6513839, +30 6947424452 http://users.ntua.gr/el04019/Homepage/Home.html -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://sos.ece.cmu.edu/pipermail/simflex/attachments/20090511/4c8776af/attachment.html>
