On 2013-04-10 20:55, Larry Baker wrote:
On 10 Apr 2013, at 11:22 AM, <simh-requ...@trailing-edge.com
<mailto:simh-requ...@trailing-edge.com>> <simh-requ...@trailing-edge.com
<mailto:simh-requ...@trailing-edge.com>> wrote:
2> Assuming that the MASSBUS hardware devices actually supported the
extended configuration, you could certainly add the extra components
into the configuration. The question then becomes do any of the
operating systems that ran on the original hardware support the
extended configuration? If the operation systems don't support the
extensions, then adding the extra simulated components is a waste of
time. Otherwise, you just have to ask yourself "Is it worth the
effort?" Note that any new components added to a simulation should be
disabled by default for compatibility with older scripts.
RXS-11M-Plus did a very nice job of supporting multiple MASSBUS
controllers. Not only that, it supported mixed-MASSBUS configurations
-- tapes and disks on the same controller. And, multi-path MASSBUS
configurations to dual-port disk drives. Our PDP-11/70 had several
MASSBUS disk drives all dual-ported to two MASSBUS controllers.
RSX-11M-Plus issued seeks separate from data transfers. Whichever
controller was available could be used to issue any command to any drive
it could reach. As I recall, the PDP-11/74 could have even more than 4
MASSBUS controllers, because each processor had its own MASSBUS/UNIBUS.
Some rather powerful disk configurations could be configured.
RSX-11M-Plus had all the code to make it work. (The developers used a
PDP-11/74 system.)
M+ supports up to 4 CPUs, 12 Unibuses, and 16 Massbuses. The 4 CPUs are
a limitation of the IIST, unless I remember wrong. The 16 Massbuses are
a logical extension from the four CPUs, since in the 11/74 was more or
less a modified 11/70, and each 11/70 can have four RH70 controllers.
The 12 Unibuses are a design limitation in RSX, as you have one
additional field in many data structures, called the Unibus run mask (or
URM). That is a 16-bit value, and thus you have one bet per Unibus. Each
CPU have one implied Unibus, leaving space for 12 additional Unibuses in
the URM.
In reality, this worked by having Unibus switches (DT07), between
segments of the Unibus. And segments could be moved from one CPU to
another. So, the buses could be reconfigured on the fly of a running
system. But all buses had to end up at one CPU or another sooner or
later. And no, you could not simultaneously have one Unibus connected to
multiple CPUs. But in case of CPU failures, you could switch the bus
over to another CPU.
(Yes, 11/74 machines are really fun, but simh probably needs some larger
reworking before you could do something like an 11/74.)
Johnny
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